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I was making a core file for FuseSoc icm with ghdl for the neorv32.
Since the neorv32 makes use of the library called "neorv32" the core file required a "logical_name: neorv32".
As experiment I plac…
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Hi,
Your blog has very interesting information, I'm stating with FPGA and helped me a lot. I have a Tang Nano 4K.
I'm starting using this FPGA boards, I'm a bit newbie with all this FPGA, I was…
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Hi,
I am trying to simulate de0-nano-test-setup using Questa Intel FPGA Edition but the compilation fails, saying it can't find neorv32_application_image.vhd. The file is definitely in the right pl…
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Hi,
I analyzed the VHDL code from your NEORV32 project with Linty: https://oss.linty-services.com/dashboard?id=neorv32&codeScope=overall
Do not get scared by the number of issues :-)
It's just …
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**Describe the bug**
Hello,
When I replaying the floating_point_test, I came across an error on converting a float to a signed integer.
It seems that the rounding of values exceeding 32 bits with…
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Hello there,
when executing following command in the litex-boards directory, the NEORV32 CPU Type is compiled and flashed to my Arty A7-100T:
`./digilent_arty.py --variant=a7-100 --cpu-type=neorv3…
vogma updated
8 months ago
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Hi,
I analyzed the VHDL code from your surf project with Linty: https://oss.linty-services.com/dashboard?id=surf&codeScope=overall
Do not get scared by the number of issues :-)
It's just to pro…
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Cloned the `riscof` framework via the command which went smoothly:
```zsh
pip3 install git+https://github.com/riscv/riscof.git
```
However, running `riscof` via the command:
```zsh
riscof --ve…
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with #619 providing some background, here's a proposal for adding a new `CAS_EN` generic to `neorv32_cpu` (with a default value of `false` for backward-compatibility).... if `CAS_EN
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# Context:
To load a `.C` program to NEORV32 first we must compile it.
There are many alternatives to make this.
## Custom GCC location:
### Steps:
- First, download GCC custom with RISC…