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hello! i have a bladerf x40 that seems to boot fpga(3 leds at bottom lit green), but all communication to the fpga fails between the fx3 and the fpga with a time out. bladerf -v debug -i doesn't give …
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Hello everyone,
I am encountering some issues about perfoming fastlock profiles within Nios II. As described in "bladerf2_common.h" from line 270 to line 274, it seems it can also be performed with…
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Hello alfikpl! I hava noticed that "memcpy(dst_ptr, sector_buf, current_size);" in main.cpp line 291! I also viewed the java source code SDGenerator.java. I found the address "dst_ptr" would equal 0xF…
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**_Reported by Andrew Boie:_**
```
qemu_nios2 tests/kernel/test_errno/test FAILED: timeout
--------------------sanity-out/qemu_nios2/tests/kernel/test_errno/tes…
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**_Reported by Andrew Boie:_**
```
qemu_nios2 tests/kernel/test_errno/test FAILED: timeout
--------------------sanity-out/qemu_nios2/tests/kernel/test_errno/tes…
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**_Reported by Andrew Boie:_**
Initial Zephyr bring-up on Nios II only targets non-vectored Internal Interrupt Controller. As a designer of a system using Nios II and Zephyr, I may need Zephyr suppor…
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Could you provide some instructions for getting the nios_ddr3 example running?
I am not familiar with the Quartus II toolset and I'm primarily interested in developing software for the Nios II proces…
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**_Reported by Andrew Boie:_**
Initial Zephyr bring-up on Nios II only targets non-vectored Internal Interrupt Controller. As a designer of a system using Nios II and Zephyr, I may need Zephyr suppor…
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Hi there,
i need to implement an synthesizer, which should be controlled by the fpga. We bought the bladerf-micro thinking, that this interface would be doable at the expansion port.
Unfortunately, …
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**_Reported by Andrew Boie:_**
As a developer, I would like to add MPU support to Zephyr so that I can mark memory regions as instructions, read-only data, or read-write data. This should improve the…