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- El procesador no soporta 200MHz. Se comporta correctamente con 100MHz
- Picosoc.v presenta instanciaciones de ejemplo para conectar perifericos en el procesador
- Asegurarse de que las señales est…
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The firmware that you use for this demo seems to be different from the regular picosoc software. Are there instructions for generating it (for example to customise the baud rate)
jrrk2 updated
2 years ago
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There is a yosys-vivado toolchain failure in one of the test projects, which is causing CI to fail. This is most probably due to the latest yosys package, which has been updated to use upstream yosys:…
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I just replace the picosoc.v with picoramsoc.v in the directory /picosoc, and remove the unused ports in hx8kdemo.v and disconnect the spiflash in hx8kdemo_tb.v before simulation. Using the same hex f…
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When I attempt to build the PicoSoC demo by running `TARGET="arty_100" make -C picosoc_demo`
it initially appears to build the example but then I get his error:
`Successfully finished Verilog fr…
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The [SymbiFlow project](https://symbiflow.github.io) is using [PicoSoC](https://github.com/cliffordwolf/picorv32/tree/master/picosoc). This is a "Cortex M0" style 32bit RISC-V processor + supporting i…
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(I never dealt with Verilog before, I'm a software dev)
At https://github.com/cliffordwolf/picorv32/tree/master/picosoc (`README.md`) I see
> `make hx8ksim`
> `make hx8kprog`
I get:
> `yosys-co…
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In picosoc.v, I noticed that the read data outputs (rdata1, rdata2) of "module picosoc_regs" are combination out, directly implemented using wire "assign".
Does this mean the read delay of picosoc_…
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It looks like it should be possible to get TinyGo running on an FPGA softcore without too much trouble.
I was reading this article earlier that describes using linker scripts for the HiFive1 and star…
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Hi, first of all I'm really glad you made this wrapper as it provides a starting point and reference for a FPGA noob like me to start modifying picosoc verilog codes. Thank you for creating this repo!…