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In PR #74, we design [vendor extension is guarded by vendorID](https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74#issuecomment-2128844747). However, here we missed some cases like:
1. A SoC v…
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WDYT? Is this publication in scope?
```
@inproceedings{Ge_2019,
author = {Ge, Jingquan and Gao, Neng and Tu, Chenyang and Xiang, Ji and Liu, Zeyi},
booktitle = {2019 IEEE 37th International Conferen…
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WDYT? Is this publication in scope?
```
@inproceedings{Ravi,
author = {Ravi, S. and Raghunathan, A. and Chakradhar, S.},
booktitle = {17th International Conference on VLSI Design. Proceedings.},
co…
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WDYT? Is this publication in scope?
```
@inproceedings{Milan_2023,
author = {Milan, Raphaële and Bossuet, Lilian and Lagadec, Loïc and Lara-Nino, Carlos Andres and Colombier, Brice},
booktitle = {20…
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WDYT? Is this publication in scope?
```
@article{Ge_2024,
author = {Ge, Jingquan and Zhang, Fengwei},
doi = {10.1109/tcad.2024.3392082},
issn = {1937-4151},
journal = {IEEE Transactions on Compute…
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I am debugging a PCIE issue using the Icicle board.
- For one setup I connected a StarTech PEX1394B3 mini-PCIE card to the Icicle, and built a Linux image with the drivers for it.
- For another …
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Hi,
I wanted to replicate a Litex soc with a Vivado block design. I was wondering if there is any way to generate a UartLite module without anything else included since the Litex UartLite control r…
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I just got a sample of a Feed Sync disposable vape with Bluetooth and touchscreen functionality.
I have disassembled the vape and found that it is based on a JL7012F6 SoC with 16M of SPI Flash and a …
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- [ ] #22
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Hardware Model v2, https://github.com/zephyrproject-rtos/zephyr/issues/51831 introduces a new scheme for boards.
A `board.yml` is used to describe meta data of the board, for example:
```
board:
…