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riscv-non-isa
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riscv-c-api-doc
Documentation of the RISC-V C API
https://jira.riscv.org/browse/RVG-4
Creative Commons Attribution 4.0 International
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Fix markdown preview
#84
zqb-all
closed
2 days ago
0
Fix typo: Intrisics -> Intrinsics
#83
wangpc-pp
closed
5 days ago
0
Migration to RISC-V specifications template in asciidoc
#82
apazos
opened
1 week ago
0
__builtin_riscv_pause not listed in document
#81
KaiYG
opened
3 weeks ago
1
Update __riscv_misaligned_* macros to refer to scalar only
#80
topperc
closed
1 week ago
1
Add atomic intrinsics
#79
wangpc-pp
opened
1 month ago
2
Remove Compiler Command-Line Arguments section
#78
kito-cheng
closed
1 month ago
0
Change branch from "master" to "main"
#77
kersten1
closed
2 months ago
3
Add a preprocessor definitions to indidcate the landing pad labeling …
#76
kito-cheng
opened
2 months ago
0
Propagation of target attributes when inlining
#75
cmuellner
opened
2 months ago
1
[FMV] Runtime Resolver Function
#74
BeMg
opened
3 months ago
18
Should we have a separate _riscv_misaligned* for scalar/vector?
#73
topperc
opened
3 months ago
8
[RFC] Function multiversion resolver function implementation
#72
BeMg
opened
3 months ago
2
Why were the __riscv_m, ... macros deprecated, will there be an alternative?
#71
camel-cdr
closed
3 months ago
2
wrong ntl preload
#70
jnk0le
opened
3 months ago
0
Using vector intrinsics with `__attribute__((target("arch=+v")))`
#69
camel-cdr
opened
5 months ago
4
Function attribute for standard fixed-length vector calling convention variant
#68
kito-cheng
opened
5 months ago
3
Function attribute for standard vector calling convention variant: riscv_vector_cc
#67
kito-cheng
closed
3 months ago
5
Document constraint "s"
#66
MaskRay
closed
5 months ago
4
Add missing `__riscv_q` predefine to riscv-c-api.md
#65
frobtech
closed
6 months ago
0
Mismatched base ISAs in target attribute arch
#64
lukel97
closed
6 months ago
4
Fix typo
#63
visitorckw
closed
6 months ago
1
Add -m[no-]unaligned-access
#62
wangpc-pp
closed
5 months ago
4
Fix typo: replace errof with error
#61
BeMg
closed
7 months ago
0
Bitmanip intrinsics: Fix orc_b_32 emulation comment for rv64
#60
cmuellner
closed
7 months ago
1
Fix the __riscv_clmul* intrinsics.
#59
Liaoshihua
closed
7 months ago
1
Fix the __riscv_sha512sum0/1 intrinsics for RV32.
#58
topperc
closed
7 months ago
0
Rework the extension test macros section
#57
cmuellner
closed
5 months ago
1
Added support for zimop extension
#56
JivanH
closed
7 months ago
5
Add zicsr and zifencei to extension test macros
#55
hasheddan
closed
8 months ago
1
vget for fractional register doesn't exist
#54
howjmay
closed
8 months ago
10
Prestacked annotation proposal
#53
jnk0le
opened
8 months ago
12
Add support for RV64E and LP64E
#52
a4lg
closed
7 months ago
10
Should the macro __riscv_c and __riscv_compressed defined for Zca?
#51
KaiYG
closed
3 weeks ago
5
Support for C operators on RVV types
#50
jacquesguan
opened
11 months ago
6
Clarify that slow misaligned accesses may be very slow
#49
aswaterman
closed
11 months ago
0
Function multi-version proposal
#48
BeMg
closed
1 week ago
6
zihintntl Intrinsic function proposal
#47
BeMg
closed
12 months ago
13
Locality for prefetch built-in proposal
#46
BeMg
closed
7 months ago
6
Document operand modifier
#45
kito-cheng
closed
9 months ago
2
Scalar bitmanip and crypto intrinsics proposal
#44
topperc
closed
8 months ago
18
Constraints for vector tuple types
#43
nick-knight
opened
1 year ago
6
Save CSRs in interrupt functions
#42
palmer-dabbelt
closed
3 months ago
1
Prevent 2 underscores from being interpreted as italics
#41
topperc
closed
1 year ago
0
Add macros for unaligned access
#40
vineetgarc
closed
1 year ago
7
Introduce new constraint for register pair
#39
kito-cheng
opened
1 year ago
1
Add inline asm operand constraints for vector register
#38
kito-cheng
closed
1 year ago
2
Asm constraint to require an even register
#37
asb
opened
1 year ago
2
Intrinsic Support for BF16 Extension
#36
joshua-arch1
opened
1 year ago
1
Adding target attribute for function.
#35
kito-cheng
closed
8 months ago
19
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