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Hi,
I was wondering if there are any plans for other FPGA ports. I'd mostly be interested in Zedboard and ZCU102.
In the past these ports (and softcores as standalone projects in general) have bee…
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I'd like to migrate a MPSoC (Ultrascale) project to 4.x, but
https://github.com/FreeRTOS/FreeRTOS-Plus-TCP/blob/main/source/portable/NetworkInterface/xilinx_ultrascale/NetworkInterface.c
is not…
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# Bug Description
In March 2024 I successfully built and run OP-TEE on an Xilinx Zynq Ultrascale+ ZCU104 board. Building a current version (4.2.0 or 4.3.0 or `master`) causes the boot to fail with …
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- **CPU**: Quad Core ARM Cortex-A53 (ARMv8-A)
- **GPU**: Mail 400 MP2
- **Memory**: > 2GB
- **Storage**: QSPI / SDCARD / SATA
- **Features**: Gb Ethernet, USB 2/3, Display Port, HDMI, USB UART
*
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ghost updated
8 years ago
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**Multiply Benchmark**
[multiply.zip](https://github.com/user-attachments/files/16336975/multiply.zip)
*220 is the total (maximum) number of DSP48E1 slices on the PYNQ Z2, so reaching 220 means …
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Hi. I succses used this project with a little bit modifications for 10G ethernet kintex7. Now I want to apply ip ten_gig_pcs_pma_0.xci for ultrascale. The specification PG068 states that I should use…
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Are there any plans to add support for the Zynq UltraScale+ family in the near future?
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`prim_xilinx_ultrascale_pad_wrapper` supports input disabling (since PR #23042) but for bidirectional pads currently implements it with a logic assignment. (For input-only and analog pads, physical in…
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`json2dcp` has not been maintained for some time but could be useful for post-placement/routing validation and DRC in Vivado. While replacing deprecated RapidWright API is fairly straightforward, it w…
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https://www.amd.com/en/products/system-on-modules/kria/k26/kr260-robotics-starter-kit.html
I'm currently working with this board which is based on a Ultrascale+ device.
I'll try to push an initi…