byuccl RapidSmith2 issues

byuccl / RapidSmith2

RapidSmith2 - the Vivado successor to RapidSmith. Released Jan 4, 2017.

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issues

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Unable to verify my Rapidsmith installation

#387 sandeeprpandey opened 4 years ago
10
Various Router and Maverick Related Changes

#386 DallonTG closed 4 years ago
0
Resolve duplication of efforts with Lut Routethroughs and Pseudo VCC Pins

#385 DallonTG opened 4 years ago
0
Helpful Router Methods

#384 DallonTG closed 4 years ago
0
Fasm Interface

#383 DallonTG closed 4 years ago
0
Capability to import and export RM RSCPs and TCPs

#382 DallonTG closed 4 years ago
0
Methods to get wires in a node + extra XDCConstraint constructor

#381 DallonTG closed 5 years ago
0
GitIngore Update: Ignore more IntelliJ files, out/, and all .Xil files

#380 DallonTG closed 5 years ago
0
Export EDIF Net Properties and don't touch LUT routethroughs

#379 DallonTG closed 5 years ago
0
Route String Tree Class

#378 DallonTG closed 5 years ago
0
Partition Pin Class

#377 DallonTG closed 5 years ago
0
Get 7 Series bonded sites with true site names

#376 DallonTG opened 5 years ago
0
PartialDeviceTest Failing with OpenJDK 11

#375 DallonTG opened 5 years ago
0
Separate staticSourceBels into vccSourceBels and gndSourceBels

#374 DallonTG closed 5 years ago
0
Edif Tools and Edif Interface Updates

#373 DallonTG closed 5 years ago
0
Removed IWIRE/OWIRE from partial device files

#372 DallonTG closed 5 years ago
0
Yosys Interface, Abstract Edif Interface, CARRY4 transformation

#371 DallonTG closed 5 years ago
0
Include common hidden macros in Cell Library

#370 DallonTG opened 5 years ago
0
Revert #365 and only flatten placed macros in EDIF export

#369 DallonTG closed 5 years ago
0
Partial Device Generator and Installer

#368 DallonTG closed 5 years ago
0
Create EDIF RPMs for all macros

#367 DallonTG opened 5 years ago
0
Travis CI build info missing

#366 DallonTG opened 5 years ago
3
Create EDIF RPMs for LUTRAM macros

#365 DallonTG closed 5 years ago
0
Design not implementable when only imported and exported but not changed

#364 mthoonen closed 5 years ago
16
Manual Intrasite Routing (for slices)

#363 DallonTG closed 5 years ago
2
Memory pin mappings

#362 nelsobe closed 5 years ago
0
Changed verson to 2.3-SNAPSHOT in build.gradle

#361 nelsobe closed 5 years ago
1
Travis fixes

#360 trharoldsen closed 5 years ago
0
Edif Interface: handle bus ports with multiple sets of brackets

#359 DallonTG closed 5 years ago
0
ImportExportExample throws ParseException with various designs

#358 RickvanLoo closed 5 years ago
3
Dynamic Pin Mappings contain nc when no connection exists

#357 trharoldsen closed 5 years ago
3
Support for RAMB36E1 and FIF036E1 dynamic pin mappings

#356 trharoldsen closed 5 years ago
0
No bels matched *RAMB36E1 when creating pinmapping.

#355 trharoldsen closed 5 years ago
4
RS2: BSCAN primitive definition not found! Please add this file and rerun.

#354 amitkulkarnis closed 5 years ago
5
RapidSmith2 support for Virtex UltraScale+ XCVU9P-L2FLGA2104 Device

#353 amitkulkarnis opened 5 years ago
1
Net properties not included in EDIF

#352 DallonTG opened 6 years ago
0
Include intrasite routing commands in TCP

#351 DallonTG closed 5 years ago
1
Fixed issue with EdifInterface printing incorrect properties in netlist.edf

#350 grigg3 closed 6 years ago
0
Zynq family files & device files for xc7z020clg400

#349 DallonTG closed 6 years ago
0
TCP writer only write edif properties to edif (Issue 338)

#348 grigg3 closed 6 years ago
1
Role of RS2 and RapidWright

#347 trharoldsen opened 6 years ago
1
Cases for bi-directional pin wires for compressed XDLRCs

#346 DallonTG closed 6 years ago
0
XDC constraints interface & XDC Constraint Package Pin

#345 DallonTG closed 6 years ago
0
"Duplicate" LOCK_PINS properties in TCP export

#344 DallonTG closed 5 years ago
1
reverseRouting naming inconsistency

#343 DallonTG opened 6 years ago
2
Added CIN as possible BEL pin for CARRY4.CI pins.

#342 trharoldsen closed 6 years ago
0
Updated release notes for V2.0.0

#341 DallonTG closed 6 years ago
0
Improved XDLRC parsing and much faster device file generation (2)

#340 nelsobe closed 6 years ago
0
Carry4 CI cell pin maps to CYINIT pin and not CI pin on BEL.

#339 trharoldsen opened 6 years ago
0
TCP writer writes user properties to edif

#338 trharoldsen closed 6 years ago
1