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not sure how easy or hard this would be, but screenshot below shows the "Further Information" section from recent Viet Nam email:
![image](https://github.com/user-attachments/assets/0f10497b-f99d-4…
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I'm trying to use axidma_display_image to display an image (bitmap image 640 x 480 x 32) on the DISPLAY attached on HDMI to my ARTY-Z7-20. The FPGA base design is the one in https://github.com/Digilen…
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Hi,
Is there/can you provide documentation on how to use the DMA Controller as a target for an AXI4-Stream.
In this case, I am using the DMA controller in Renode. I am streaming data to the AXI4-S…
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Devlopers I am trying to use this tool for my personal OPC_UA project. I want to create a instance model using nodsets released by Euromap organisation. I am attaching the link for downloading nodeset…
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I did just a short test, but get a read timeout, see below. Do I need to change the example code somehow?
```
root@te0715_linux:~# modprobe xilinx_axidma
xilinx_axidma: loading out-of-tree module t…
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Hello,
I found that read access to the Rx memory allocated by the driver is slow too.I have already referred to the issue:[https://github.com/bperez77/xilinx_axidma/issues/69](url)
In my app,i dis l…
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Hi!
As I understand the benchmark example program should also work for a VDMA engine looped back, correct? I have a design which contains only a VDMA engine with TX and RX looped back. The module l…
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When using the driver with a VDMA core with more than one framebuffer (e.g., with xlnx,num-fstores = ), the frame buffer addresses beyond the first are not configured.
This is the lines which seem …
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I need about 100MB of vdma buffers.
I wondered... Does it make performance wise a difference if I make one udmabuf with 100mb or 5 with 20mb each?
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Hey,
can you please specify on which version of the VDAM5050 these messages are based..?
Thank you!