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**Environment**
v3.27.0
**Describe the bug**
The following classification tests inputs do not have a corresponding output and/or are in the wrong place, and are therefore not tested:
- ./tests/s…
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ghdl -a --std=08 --work=osvvm OSVVM/AlertLogPkg.vhd
OSVVM/AlertLogPkg.vhd:115:1:warning: package "alertlogpkg" was also defined in file "OsvvmLibraries/osvvm/AlertLogPkg.vhd" [-Wlibrary]
OSVVM/Aler…
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I was making a core file for FuseSoc icm with ghdl for the neorv32.
Since the neorv32 makes use of the library called "neorv32" the core file required a "logical_name: neorv32".
As experiment I plac…
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**Environment**
Latest main, git hash:
```
dd647776503a1a4bb0f4be6c844b8394e38dc106
```
**Describe the bug**
I've discovered that we now have two rules governing the indentation of null statem…
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### Windows Version
10.0.22631.4169
### WSL Version
2.3.24.0
### Are you using WSL 1 or WSL 2?
- [X] WSL 2
- [ ] WSL 1
### Kernel Version
5.15.153.1-2
### Distro Version
ubuntu 24.04
### Oth…
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### Official FAQ
- [X] I have checked the official FAQ.
### Ventoy Version
1.0.96
### What about latest release
Yes. I have tried the latest release, but the bug still exist.
### Try alternative…
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Assume having a package in a file `pkg_a.vhd`:
```vhdl
package pkg_a is
type my_type_t is (A, B, C)
end package pkg_a;
```
and a second package `pkg_b` in a file `pkg_b.vhd` which scop…
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Hi,
our students use edaplayground the following way:
* Add (Upload) a testbench file and some entities+architecture files to a playground
* Leave the default design.vhd and testbench.vhd empty
…
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The **Error Message** i get is
> own_periphs/uart/UART_1.v:1: ERROR: Re-definition of module `$abstract\uart_clk_div_17_1'!
When i try to instantiate multiple of the same cores, in the **Target …
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https://github.com/open-logic/open-logic/blob/8f50f5477dff628ac690eb5e8ec9915bdd8a1bec/src/axi/vhdl/olo_axi_master_simple.vhd#L312
I am trying to use the simple AXI4 master. Unfortunately, on line …