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# Description
Create a DFF register that can hold variable length state values.
It should be instantiated as the examples in the book:
`STATE_REG: vDFF generic map(STATE_WIDTH) port map(clk, ne…
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GHDL master in our experimental tool CI bucket seems to fail on a wide range of tests, e.g.:
```
make[4]: Entering directory '/home/runner/work/cocotb/cocotb/examples/simple_dff'
mkdir -p sim_bui…
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The VHDL Vivado example fails to generate the Vivado project with Vivado 2022.1:
```
PS C:\git\vunit\examples\vhdl\vivado> python generate_vivado_project.py
vivado -nojournal -nolog -notrace -mode …
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**Feature Description** :
Let user add a list of files for which no errors/warnings should be raised.
**Feature Usecase** :
Defining libraries in "vhdl_ls.toml" which raise tons of errors due…
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Hi,
I analyzed the VHDL code from your PoC project with Linty: https://oss.linty-services.com/dashboard?id=poc&codeScope=overall
Do not get scared by the number of issues :-)
It's just to provi…
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The documentation of GHDL contains a brief [Quick Start Guide](https://ghdl.github.io/ghdl/quick_start/index.html) to introduce GHDL's CLI interface to users, but it does not contain an introduction t…
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Ref: [Multi-root workspaces](https://code.visualstudio.com/docs/editor/multi-root-workspaces) where mentioned in [#5](https://github.com/ghdl/ghdl-language-server/issues/5#issuecomment-503262439).
…
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even the examples like the or gate VHDL is no working for me, any solutions?
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In many VHDL examples such as _check_ the `runner_cfg` generic has the `runner_cfg_default` default value. This generic value includes the simulation output path based on the run.py file location (vun…
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It would be nice to give our HDL coding examples a uniform style. Ideally, we can find two style guides which are similar between VHDL and Verilog.
For Verilog I'd go with https://github.com/lowRIS…