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**Description**
After compiling ALL Xilinx libraries I discovered that a lot of in the XIlinx libraries available components are not compiled in the GHDL libraries.
Maybe I'm doing something wrong? …
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Hi,
I have a problem with entity name clashing with port name. My code is compiling with Modelsim but not GHDL. Here is the component interface:
```
entity ami_write is
port(
clk …
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We're currently replacing periods with underscores and performing rudimentary collision detection. However, I don't think this technique is very robust and wont scale well when we start to support cra…
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I am using the latest GHDL from github.
I built unisim with
```
compile-xilinx-vivado.sh --unisim --source /tools/Xilinx/Vivado/2022.2/data/vhdl/src
```
then I ran
```
ghdl -m -g -Pxilinx-v…
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https://wmchappy.cn/2015/07/31/jsjl-AMBA/
AMBA 协议交流～
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For testing with netlists I need some vendor libraries. These are shipped with the simulator ActiveHDL and I use this to include them
```
vu.add_external_library('pmi_work', activehdl_lattice_path /…
ghost updated
4 years ago
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## Description
The generated code of the entity uses the types t_array_elem0 / t_array_elem1/t_array_elem2, which do not exist in the associated package.
I am also wondering what multidimensional …
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---
Author Name: **Sebastien Van Cauwenberghe**
Original Redmine Issue: 380 from https://www.veripool.org
Original Date: 2011-03-01
Original Assignee: Sebastien Van Cauwenberghe
---
Work is ongoi…
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**Description**
While attempting load a design into yosys via the GHDL plugin I get a storage error.
**Expected behaviour**
I expect the design to successfully parse, continue through yosys synth…
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I'm reviewing the automatically generated documentation and found that sometime the inheritance diagram is missing:
![image](https://cloud.githubusercontent.com/assets/956109/20460694/b6391730-aeeb-1…