issues
search
CTSRD-CHERI
/
cheri-specification
CHERI ISA Specification
Other
23
stars
7
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
Added CID Sealing section in experimental
#76
francislaus
closed
1 year ago
0
RISC-V: Tidy description of capability encoding mode
#75
bsdjhb
closed
1 year ago
0
Update xCCSR for V9
#74
bsdjhb
closed
1 year ago
2
move store capability to tag clearing if the store cap permission isn't set
#73
tariqkurd-repo
opened
1 year ago
1
Nothing is written, yet, no. In part I think this would be part of a larger effort to evaluate more recent changes to the privileged spec. There are some important lessons to be learned here from Morello which requires bounds to cover the entire cache line which is not ideal. Probably you just want the bounds to overlap with at least part of the region you are flushing (at least for flush and prefetch) as the actual write was already validated and flush is just changing the "timing" of a commit, and similarly for prefetch the actual read will be validated in the future.
#72
tariqkurd-repo
closed
1 year ago
0
Debug specification for CHERI-RISC-V
#71
andresag01
opened
1 year ago
1
CHERI privilege level enable
#70
tariqkurd-repo
opened
1 year ago
5
CHERI global enable/disable
#69
tariqkurd-repo
opened
1 year ago
5
Define instruction outputs for non-derivable capability inputs
#68
andresag01
opened
1 year ago
14
Interconnect support for RISC-V AMOSWAP.C
#67
andresag01
opened
1 year ago
2
Merging CHERI exception priorities with standard RISC-V exceptions
#66
tariqkurd-repo
opened
1 year ago
7
CHERI specification for RISC-V Cache Management Extension
#65
andresag01
opened
1 year ago
11
Merge CSR and SCR address spaces in RISC-V
#64
andresag01
opened
1 year ago
0
Expand c.mv to CMove
#63
tariqkurd-repo
opened
1 year ago
1
Add easy mode switch instruction
#62
tariqkurd-repo
opened
1 year ago
1
Add an additional paragraph to the 64-bit CHERI format description.
#61
bsdjhb
closed
1 year ago
0
riscv: Update the main CHERI-RISC-V chapter for mode-dependent jumps.
#60
bsdjhb
closed
1 year ago
1
riscv: Make the scratch SCRs extend the base scratch CSRs.
#59
bsdjhb
closed
1 year ago
0
Trim some stale things from the RISC-V chapter
#58
bsdjhb
closed
1 year ago
0
V9 changes
#57
bsdjhb
closed
1 year ago
0
x86: Deprecate most segment prefixes entirely in capability mode.
#56
bsdjhb
closed
1 year ago
0
Deprecate or remove several CHERI-RISC-V instructions
#55
bsdjhb
closed
1 year ago
0
RISC-V CHERI exception priority table doesn't include PCC unaligned base
#54
bsdjhb
closed
1 year ago
5
RISC-V: Remove DDC/PCC offsetting entirely for now.
#53
bsdjhb
closed
1 year ago
3
x86 Capability Flags instructions
#52
bsdjhb
closed
1 year ago
1
X86 Tag stride instruction fixups
#51
bsdjhb
closed
1 year ago
0
x86: Don't set ZF for various GC* instructions.
#50
bsdjhb
closed
1 year ago
1
Fix most undefined references
#49
arichardson
closed
1 year ago
0
Encoding conflict
#48
tariqkurd-repo
opened
1 year ago
4
Removing DDC offsetting entirely before CHERI-RISC-V standardisation?
#47
rwatson
opened
1 year ago
10
x86: Add [GS]CHI and GCLIM.
#46
bsdjhb
closed
1 year ago
1
X86: Rationale sections for additional arithmetic instructions and tags in vector registers
#45
bsdjhb
closed
1 year ago
0
x86: Rework use of the term deprecate.
#44
bsdjhb
closed
1 year ago
0
x86: Remove far branches from capability mode.
#43
bsdjhb
closed
1 year ago
0
X86: Extend INC and DEC to support capability operands
#42
bsdjhb
closed
1 year ago
0
Version 9 changes
#41
bsdjhb
closed
1 year ago
1
Remove references to PCC/DDC offseting in the architecture chapter.
#40
bsdjhb
closed
1 year ago
0
Remove offsetting from CHERI-x86
#39
bsdjhb
closed
1 year ago
0
Use ubuntu-latest for GitHub CI actions.
#38
bsdjhb
closed
1 year ago
1
x86: Use capability-wide variant of CMPC for capability comparisons.
#37
bsdjhb
closed
1 year ago
0
X86 opcodes
#36
bsdjhb
closed
1 year ago
1
x86: Remove CGetSealed.
#35
bsdjhb
closed
1 year ago
0
Make DDC/PCC offsetting an optional feature rather than mandatory
#34
bsdjhb
closed
1 year ago
1
x86: Remove CGetAddr.
#33
bsdjhb
closed
1 year ago
0
x86: Mark other status flags in RFLAGS undefined.
#32
bsdjhb
closed
1 year ago
2
X86 lea
#31
bsdjhb
closed
1 year ago
0
x86: Renumber capability fault error codes.
#30
bsdjhb
closed
1 year ago
2
Fix trailing whitespace and add a pre-commit hook
#29
arichardson
closed
1 year ago
0
Add more prose on direct memory-offset MOVs.
#28
bsdjhb
closed
1 year ago
0
Make the CHERI exception codes architecture-specific.
#27
bsdjhb
closed
1 year ago
2
Previous
Next