Digilent vivado-boards issues

Digilent / vivado-boards

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issues

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system clock of IP design is not working on the vivado 2024.1

#46 eeric9655 opened 2 weeks ago
0
Not able to Add Kintex-7 FPGA (XC7K325T-2FFG900C) board files in the Vivado 2022.1 version

#45 Damodartampula opened 8 months ago
0
Zybo: Corrected CPU PLL settings

#44 emb4fun closed 1 year ago
0
Vivado-board tab missing in Vivado 2023.1

#43 jkmchow opened 1 year ago
1
@mohanex correcting uart pins on nexys video

#42 mohanex opened 1 year ago
0
USING FPGA

#41 K4RAS opened 1 year ago
0
nexys video: fix on-board led io standard config

#40 Headcrabed opened 1 year ago
0
Error while C synthesis on Vitis HLS 2020.1 for Arty A7-35T

#39 SuperChamp234 opened 1 year ago
0
Zedboard MDIO on EMIO

#38 johnmmower opened 1 year ago
0
added 2 mig modes, added ddr3 interface to board, fixed clk_wiz probl…

#37 ColdfireMC opened 2 years ago
0
Zybo board files error on Ubuntu

#36 1c3t3a closed 2 years ago
2
Looking for Basys2 board files

#35 yalla closed 3 years ago
1
Increment Genesys ZU-3EG revision B.0 file version

#34 artvvb closed 3 years ago
1
Added board files for the NetFPGA 1G CML

#33 bkzshabbaz opened 3 years ago
0
Arty Z7 Part0_Pins Wrong

#32 bsparkm opened 3 years ago
1
Added Zybo Z7 10 board image and updated xml file

#31 hbelatikar closed 3 years ago
1
Zedboard PS_CLK frequency incorrect

#30 elodg closed 1 year ago
1
SPI Slave mode SS pin not connected right

#29 RupertAmann opened 4 years ago
0
The part number syntax was updated for Arty-A7-100. Previously, with …

#28 timothystotts opened 4 years ago
1
Missing mig.prj File for Genesys ZU-3EG Board

#27 JohnStratoudakis closed 4 years ago
1
issues with ZYNQ7 Processing System

#26 khaidz closed 3 years ago
1
zybo: fix PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY error in Vivado.

#25 svet-am opened 4 years ago
1
Nexys4 board not showed with Vivado 2019

#24 andrea1984 closed 4 years ago
1
Support request for DSDB

#23 wbmrcb opened 4 years ago
0
Broken links!

#22 Neuromod closed 5 years ago
1
missing board files for Arty S7-50 revision E

#21 distractedlambda opened 5 years ago
0
Zybo Z7-20: Vivado 2018.3 reports critical warnings in DDR interface

#20 ghost closed 5 years ago
3
redundant port map in genesys2/board.xml

#19 zhutmost closed 5 years ago
1
add ZYBO files compatible with Vivado 2017.x and newer

#18 svet-am closed 5 years ago
3
Fixed Zybo preset for Eth0 MDIO pins

#17 vengin opened 5 years ago
1
How to use board supported files (device drivers) of Artix A7 in vivado.

#16 SUBANISHAIK closed 5 years ago
1
Zybo: ENET0 MDIO mapped to EMIO instead of MIO

#15 Jiware opened 5 years ago
0
Zedboard LEDs not working

#14 ARamsey118 closed 5 years ago
1
NetFPGA-1G-CML

#13 bkzshabbaz opened 6 years ago
1
Incorrect FPGA part in Arty A7-100 mig.prj file

#12 artvvb opened 6 years ago
0
Arty-s7-25 issue

#11 AdamDarkh closed 6 years ago
1
Added Vivado_init.tcl

#10 ghost closed 6 years ago
0
init.tcl is deprecated in Vivado 2017+

#9 ghost closed 6 years ago
0
Zybo Z7 preset files invalid syntax.

#8 jbootsma closed 6 years ago
2
Genesys 2 DDR3 interface impedance

#7 QrackEE closed 6 years ago
1
pynq-z1 board awareness in vivado

#6 jge64 closed 6 years ago
1
new: arty: Find better solution for GPIO/SPI conflict

#5 sbobrowicz opened 7 years ago
1
Update part0_pins.xml

#4 rjbohnert closed 6 years ago
0
PYNQ-Z1 board file

#3 ekiwi closed 7 years ago
9
new: board_files: genesys2: hdmi and USB OTG signals broken

#2 tom21091 closed 8 years ago
1
2015.3 and later

#1 tom21091 closed 8 years ago
2