FPGA-Research-Manchester FABulous issues

FPGA-Research-Manchester / FABulous

Fabric generator and CAD tools

https://fabulous.readthedocs.io/en/latest/

Apache License 2.0

148 stars 34 forks source link

issues

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Supertiles and normal tiles

#251 Sacoder0000 opened 3 days ago
7
Buffer in tiles

#249 Sacoder0000 opened 6 days ago
6
fix configuration bit problem after #242

#248 KelvinChung2000 opened 6 days ago
0
Update publications.bib

#247 ruck314 opened 1 week ago
0
Xs in Demo Project Simulation

#246 hhnurr opened 1 week ago
1
Difference in bitstream generation between master and dev branch

#245 IAmMarcelJung opened 3 weeks ago
7
FABulous: Fix default project language

#244 EverythingElseWasAlreadyTaken closed 3 weeks ago
0
Wip/listfile multipliers

#243 EverythingElseWasAlreadyTaken closed 3 weeks ago
0
Fixing non power of 2 mux generation

#242 KelvinChung2000 closed 2 weeks ago
2
Fix non power of 2 mux gen

#241 KelvinChung2000 closed 4 weeks ago
0
docs: Fix build_docs workflow and add docs dependency versions

#240 EverythingElseWasAlreadyTaken closed 2 weeks ago
0
Update Dependencies

#239 mole99 closed 1 month ago
0
RegFile: Fix assignment to read data

#238 mole99 closed 1 month ago
0
Fix UserCLK wire generation in SuperTiles

#237 mole99 closed 1 month ago
0
Dependency Revaluation

#236 mole99 opened 1 month ago
6
Fix VHDL fabric generation

#235 EverythingElseWasAlreadyTaken closed 1 month ago
0
FABulous: Extend .env default paths and update gitignore

#234 EverythingElseWasAlreadyTaken closed 1 month ago
0
Fix backward compatibility to old project structure and some housekeeping

#233 EverythingElseWasAlreadyTaken closed 1 month ago
5
Add better handling for environment variables

#232 EverythingElseWasAlreadyTaken closed 2 months ago
4
fabric_files:verilog_template:FABulous.tcl: Remove npnr parameter

#231 EverythingElseWasAlreadyTaken closed 2 months ago
0
Persistent command line history not working on FABulous2.0 branch

#230 IAmMarcelJung opened 2 months ago
3
Update python to 3.12 and update documentation

#229 IAmMarcelJung closed 2 months ago
3
Using python3.10 feature but python3.9 is specified in README.md (FABulous2.0-development branch)

#228 IAmMarcelJung closed 2 months ago
6
Add start_FABulator command to be able to run FABulator from the FABulous shell

#227 JakobTernes closed 3 months ago
13
What does the "desync_flag" parameter do?

#226 RobB720 opened 3 months ago
2
Add new print feature

#225 KelvinChung2000 closed 3 months ago
5
Feature INCLUDE keyword

#224 KelvinChung2000 closed 3 months ago
0
Warning For Individual Port Declaration

#223 A-Kibats closed 3 months ago
1
Vector Support for User BEL in Verilog.

#222 A-Kibats closed 3 months ago
0
drop vpr support and clean up

#221 KelvinChung2000 closed 3 months ago
0
Added toggle for log level + minor corrections.

#220 A-Kibats closed 3 months ago
1
Fix .fst generation in run_simulation and correct signal generation for the demo design in the test bench

#217 IAmMarcelJung closed 3 months ago
1
Configuration State Machine

#215 RobB720 opened 3 months ago
1
Vhdl simulation

#214 Biswajitks1 opened 3 months ago
17
Waveform

#213 CarlosQbit opened 3 months ago
2
Adds docs dependencies installation to README

#212 TaoBi22 closed 4 months ago
0
Fix for VHDL Project Creation Issue

#211 Biswajitks1 closed 3 months ago
1
Updates to documentation & new logger.

#210 A-Kibats closed 3 months ago
14
geometry_gen:fabric_geometry: Fix indexing error for smaller fabrics

#208 EverythingElseWasAlreadyTaken closed 4 months ago
2
ERROR: No such command: synth_fabulous (type 'help' for a command overview)

#207 CarlosQbit closed 4 months ago
10
LocalWriteStrobe output from eFPGA_Config

#206 RobB720 opened 4 months ago
2
No such file or directory: 'yosys'

#205 CarlosQbit closed 4 months ago
10
Issue with io_oeb in User Design

#204 IAmMarcelJung opened 4 months ago
5
Fix typos, grammar, spelling and factual mistakes in the documentation

#203 IAmMarcelJung closed 3 months ago
12
Vhdl synthesis

#202 Biswajitks1 opened 4 months ago
9
Switch-Matrix contains commented-out ports

#201 hoyer-ims opened 4 months ago
2
Synthesis of VHDL

#200 Biswajitks1 closed 4 months ago
3
:fabric_gen: Fix VHDL ConfigMem gets instantiated twice per tile

#198 EverythingElseWasAlreadyTaken closed 5 months ago
7
New Logger , Updated Docstrings & New Sphinx theme.

#197 A-Kibats closed 4 months ago
11
init commenting

#194 A-Kibats closed 5 months ago
1