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IObundle
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py2hwsw
a Python framework for managing embedded HW/SW projects
MIT License
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Fix py2hwsw top module
#86
arturum1
opened
4 hours ago
0
IP Core Broswer
#85
jjts
opened
1 day ago
0
new "doc-clearpage" attribute
#84
jjts
opened
1 day ago
0
csrs should accept ungrouped regs
#83
jjts
opened
1 day ago
0
Separate confs into multiple tables
#82
jjts
opened
2 days ago
0
Merge iob-soc/main, fix iob_acc, fix py2 parent bug
#81
And-Nob
closed
4 days ago
0
Add support for `doc_only` attribute in core's confs and csr_groups.
#80
arturum1
closed
6 days ago
0
Add `doc_only` attribute to confs and csr_groups; Add input validation for port suffix; Add missing suffixes in lib modules.
#79
arturum1
closed
5 days ago
1
Shorthand notation suports csrs iob_uart has the iob_csrs block as an example
#78
agrevin
closed
5 days ago
0
Add address signal to regfiles & remove `csrs_iob`; Merge iob-soc/main into py2hwsw.
#77
arturum1
closed
1 week ago
0
Add `iob_` prefix to remanining lib modules and `bsp.[v]h`
#76
arturum1
closed
2 weeks ago
0
Add `--split` flag to `makehex.py`; Fix iob_system.
#75
arturum1
closed
2 weeks ago
0
Testbench revamp
#74
jjts
opened
2 weeks ago
0
CSR internal interface for autoreg=0
#73
jjts
opened
2 weeks ago
0
Handle memories
#72
jjts
opened
2 weeks ago
0
upgrade AXI interconnect to multi-split / multi-merge architecture
#71
jjts
opened
2 weeks ago
0
Add suffix to every port
#70
arturum1
closed
5 days ago
0
Resolve github issues.
#69
arturum1
closed
2 weeks ago
1
Add `iob_` prefix to remaining lib modules and board wrappers.
#68
arturum1
opened
2 weeks ago
0
iob_system structure is wrong
#67
jjts
closed
2 weeks ago
0
use 2-tuple in connections, not n-tuple
#66
jjts
closed
2 weeks ago
0
change "interface" to "signals"
#65
jjts
closed
2 weeks ago
0
Fix bugs in cyclonev wrapper; Move `README.md` to iob-soc.
#64
arturum1
closed
3 weeks ago
0
Fix CDC problems with lib modules
#63
P-Miranda
opened
3 weeks ago
2
Fix bugs in iob_system fpga wrappers; Improve build dir Makefile clean targets.
#62
arturum1
closed
3 weeks ago
0
change BSP origin
#61
jjts
closed
2 weeks ago
0
SERIAL_PORT
#60
jjts
closed
2 weeks ago
0
Interface subtype is now infered from port/wire name
#59
agrevin
closed
3 weeks ago
0
Remove 2 least significant bits from address buses; Rename port_prefix and wire_prefix to prefix; Update README.
#58
arturum1
closed
3 weeks ago
0
Improve error messages; Add `--py2hwsw_docs` argument; Initial py2 user guide; Fix linter;
#57
arturum1
closed
4 weeks ago
0
Signals with direction must represent it by addign a suffix to its name instead of a "direction" variable
#56
agrevin
closed
1 month ago
0
prefix attribute
#55
jjts
closed
3 weeks ago
1
Add `iob_and_tb.v`; Update README.md; Update Nix; Format code.
#54
arturum1
closed
1 month ago
0
Move iob-soc lib modules into py2hwsw.
#53
arturum1
closed
1 month ago
0
fix(xsim): variables for remote simulation
#52
P-Miranda
closed
1 month ago
0
Add acknowledgement; Add SPDX license headers; Add defaults for `original_name` and `name`; Fix append of lists from child cores.
#51
arturum1
closed
1 month ago
0
Add `parent` attribute; Add bit slicing and concatenations in port connections; Add regfile in CSRs and asym FIFOs.
#50
arturum1
closed
1 month ago
0
Validate that parameter values fit within the specified range
#49
agrevin
closed
2 months ago
1
Generate internal CSR FIFOS (via python params); Add CSRs APB, AXI, AXIL support; Remove default pc-emul sources.
#48
arturum1
closed
2 months ago
1
Blocks can be instantiated with shorthand notation
#47
agrevin
closed
1 month ago
7
Add support for shorthand notation i wires and ports
#46
agrevin
closed
2 months ago
0
Shorthand notation changed to look like command line
#45
agrevin
closed
2 months ago
0
FIx ci.yml; Add missing regs in csrs module; Resolve issues.
#44
arturum1
closed
2 months ago
0
Shorthand notation supports multiple line strings, where each line adds an attribute
#43
agrevin
closed
2 months ago
0
Rename default `$(FPGA_TOP)` value and constraints
#42
arturum1
closed
2 months ago
0
ShortHand notation
#41
agrevin
closed
2 months ago
0
Resolve issue; Improve debug features; Rename FPGA files/folders.
#40
arturum1
closed
2 months ago
0
Registers are only infered when "_nxt" is present
#39
agrevin
closed
2 months ago
0
Improve `csrs` module.
#38
arturum1
closed
2 months ago
0
Add new standard python parameters; Add `print_core_dict` target.
#37
arturum1
closed
2 months ago
0
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