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Jpnock
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mips-verilog-cpu
A MIPS-I CPU implemented in SystemVerilog
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Fix typo in container registry domain
#64
p-
opened
1 year ago
0
test: Update TB to run integration tests before instruction filter instructions
#63
dharmilshah99
closed
2 years ago
0
Target iverilog v11.0, improve test scripts and re-arrange integration tests
#62
Jpnock
closed
2 years ago
0
Improve README
#61
Jpnock
closed
2 years ago
0
test: Add binary search and move location of J and JAL edge-case tests
#60
Jpnock
closed
2 years ago
0
Removes unused `src_b_sel` Signal
#59
dharmilshah99
closed
2 years ago
0
Various testing improvements
#58
Jpnock
closed
2 years ago
1
test: Check that all registers are zero after reset
#57
Jpnock
closed
2 years ago
0
control: Remove non-required temporary registers (and tidy test code)
#56
Jpnock
closed
2 years ago
0
test: Add C program test-cases
#55
Jpnock
closed
2 years ago
0
alu: Rewrite without the use of latches
#54
Jpnock
closed
2 years ago
1
Fixes Latch Inferred in mips_cpu_bus
#53
dharmilshah99
closed
2 years ago
0
Adds SLL/SLLV/SRA Tests
#52
ljd20
closed
2 years ago
3
Adds SLT/SLTI Tests
#51
dharmilshah99
closed
2 years ago
3
SLTIU and SLTU test benches added.
#50
JoachimSand
closed
2 years ago
2
control: Add byte-enables for LWL and LWR; make JAL and JALR unconditionally link
#49
Jpnock
closed
2 years ago
0
Implement LWL and LWR instructions
#48
Jpnock
closed
2 years ago
0
Edge case testing
#47
Jpnock
closed
2 years ago
1
test: Add basic tests for LB, LH and SW
#46
Jpnock
closed
2 years ago
0
control: Fix race conditions and combinational logic loops (plus add more debugging logic)
#45
Jpnock
closed
2 years ago
0
Simple Load/Store TB
#44
ptar124
closed
2 years ago
1
test: Add Branch, Jump, Shift and SUBU Tests
#43
jeanpi101
closed
2 years ago
1
Fix non-aligned loads and stores, as well as instant halting the PC is reset in specific conditions
#42
Jpnock
closed
2 years ago
0
Read operation byte-enables
#41
Jpnock
closed
2 years ago
1
Arithmetic and Logic Tests
#40
ljd20
closed
2 years ago
3
Branch and ALU fixes
#39
Jpnock
closed
2 years ago
0
Adds Waitrequest Logic
#38
dharmilshah99
closed
2 years ago
3
Avalon testing
#37
Jpnock
closed
2 years ago
0
Splits Submodule and Instruction TBs
#36
dharmilshah99
closed
2 years ago
2
Load/Store instructions (non-word alignment)
#35
Jpnock
closed
2 years ago
0
Update Control to Support ALU Instructions (and implement SLT, SLTU, MTHI and MTLO)
#34
dharmilshah99
closed
2 years ago
0
Branch instructions
#33
JoachimSand
closed
2 years ago
3
Implement load/store instructions and assemble test benches
#32
Jpnock
closed
2 years ago
0
Fixed RAM Combinatorial READ path.
#31
dharmilshah99
closed
2 years ago
0
Improve control logic and fix iverlog warnings
#30
Jpnock
closed
2 years ago
1
Adds DIV/DIVU instructions.
#29
dharmilshah99
closed
2 years ago
0
ir: Add decoded regimm output
#28
JoachimSand
closed
2 years ago
0
Test benches
#27
Jpnock
closed
2 years ago
1
cpu: Fix endianness
#26
Jpnock
closed
2 years ago
6
Restore Effective Address Signal in `rtl/mips_cpu_bus.v`
#25
dharmilshah99
closed
2 years ago
0
Halting
#24
Jpnock
closed
2 years ago
0
Halting, testbench, debug logic and fixes to the regfile and sign-extension
#23
dharmilshah99
closed
2 years ago
1
Updating PC on FETCH
#22
dharmilshah99
closed
2 years ago
8
Build fixes and automated testing
#21
Jpnock
closed
2 years ago
0
Add Docker file for building iverilog
#20
Jpnock
closed
2 years ago
1
Byte enable information
#19
Jpnock
closed
2 years ago
2
Adds Control Unit
#18
dharmilshah99
closed
2 years ago
1
Reset behaviour
#17
Jpnock
opened
2 years ago
3
Add IR
#16
jeanpi101
closed
2 years ago
0
Implement Load Word and Store Word Instructions
#15
dharmilshah99
closed
2 years ago
0
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