TUM-LIS glip issues - Githubissues

TUM-LIS / glip

Generic Logic Interfacing Project

http://glip.io

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Has anyone attempted a windows build?

#64 AlessandroAU opened 5 years ago
3
fx3_flagc_n and fx3_flagd_n of glip_cypressfx3_toplevel

#63 eiselekd closed 5 years ago
2
I am having trouble using glip_read_b function with FX3

#62 chunyen627 opened 5 years ago
3
Channel multiplexer

#61 yaorong0921 closed 6 years ago
7
UART backend: check access permissions

#60 koenenwmn opened 6 years ago
1
Dualclock fifos

#59 koenenwmn closed 6 years ago
1
Create generic multi-channel protocol

#58 imphil opened 6 years ago
4
Remove current auto-detect code from UART backend

#57 imphil opened 6 years ago
0
Create "GLIP URL" syntax to specify backend + options as one string

#56 imphil opened 6 years ago
0
UART backend: make FIFO width an option

#55 imphil opened 6 years ago
0
Fixed error in word distance calculation.

#54 koenenwmn closed 6 years ago
0
Fix timing issues in fx3 toplevel

#53 koenenwmn closed 6 years ago
0
Fix UART bugs (ALL of them (TM))

#52 koenenwmn closed 6 years ago
1
Stress test

#51 koenenwmn closed 6 years ago
0
Enable uart_get_fifo_width() to return "unknown"

#50 imphil closed 6 years ago
0
Stress test

#49 koenenwmn closed 7 years ago
1
Wait for empty write buffer before disconnecting.

#48 koenenwmn closed 7 years ago
0
UART: High FPGA -> Host traffic causes data corruption

#47 imphil closed 6 years ago
2
Fixed bug regarding empty egress_cdc fifo.

#46 imphil closed 7 years ago
0
FX3: Data corruption on heavy FPGA -> Host traffic

#45 imphil closed 7 years ago
5
Create torture tests for unidirectional communication

#44 imphil closed 6 years ago
1
[WIP] Draft FX3 firmware interface

#43 wallento opened 7 years ago
2
FX3: 32 bit protocol

#42 wallento opened 7 years ago
1
cypressfx3 has different endian-ness than UART and TCP backends in 16 bit mode

#41 imphil closed 7 years ago
3
Added 16 and 32 bit version of FX3 toplevel.

#40 koenenwmn closed 7 years ago
0
FX3: Provide real 16 bit FIFO width

#39 imphil closed 7 years ago
2
FX3: Write block size of 6 doesn't work in loopback demo

#38 imphil closed 7 years ago
2
Up-/ downscaler problems at high frequencies

#37 koenenwmn closed 7 years ago
1
FX3: Writing 1024 bytes (or a multiple of it) to doesn't reach the device

#36 koenenwmn closed 7 years ago
2
Fx3

#35 koenenwmn closed 7 years ago
1
Integrate uart dpi testbench in GLIP

#34 imphil opened 7 years ago
1
WIP: Uart ingress buffer ordering

#33 imphil closed 7 years ago
0
Improve timing of glip_upscale

#32 imphil closed 7 years ago
5
Synthesis Warning in debitor.v

#31 imphil opened 7 years ago
1
Use FIFO implementation which doesn't cause warnings in Vivado

#30 imphil closed 7 years ago
5
Uart fifo generic

#29 koenenwmn closed 7 years ago
3
XON/XOFF flow control for UART backend

#28 wallento opened 8 years ago
0
UART: Add buffer to egress path

#27 wallento closed 8 years ago
0
UART: Allow custom baud rates

#26 wallento closed 8 years ago
1
Fix cbuf race

#25 wallento closed 8 years ago
1
Changes uart

#24 imphil closed 8 years ago
1
Auto-detect UART

#23 wallento opened 8 years ago
2
delay the dpi_tcp model to mimic using UART in actual FPGA

#22 wsong83 closed 8 years ago
3
UART: Upscale and downscale

#21 wallento closed 8 years ago
0
Make TCP backend default

#20 wallento closed 8 years ago
0
Make circular buffer thread-safe

#19 wallento opened 8 years ago
7
Implement cbuf_clear()

#18 wallento opened 8 years ago
0
TCP: DPI implementation

#17 wallento closed 8 years ago
0
Fix TCP timeout handling and errors of syscalls

#16 wallento closed 8 years ago
1
loopback_measure: Partial writes on blocking

#15 wallento closed 8 years ago
4