YosysHQ / padring

A padring generator for ASICs
ISC License
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asic chip eda vlsi yosys

PADRING - a padring generator for ASICs

Build Status

This tool makes padrings for ASICs using a LEF file and a placement/configuration file. The padrings can be output in GDS2, DEF and/or SVG format. Check out the example in the example directory.

Commandline options

The filler cells are auto-detected by the padring program. Should this process fail, the user can add an explicit prefix which will be used to find the filler cells.

Multiple LEF files can be specified. During loading, existing cells with the same name will be overwritten.

Configuration file

The following commands are available:

DESIGN \<name> ;

GRID \<grid size> ;

AREA \<width> \<height> ;

CORNER \<instance_name> \<location> \<cell_name> ;

PAD \<instance_name> \<location> [FLIP] \<cell_name> ;

SPACE \<space> ;

Space between the I/O pads is distributed evenly unless a specific space between two pads is specified directly using the SPACE command.

Building

Dependencies:

Building: