YosysHQ picorv32 issues

YosysHQ / picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

ISC License

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issues

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Insert delay after release power-down SPI flash command

#167 joshtyler opened 4 years ago
0
Enable the use of 64-bit riscv tools

#166 tommythorn closed 2 years ago
4
License file missing

#165 jjts closed 2 years ago
1
Beginner question: C.JR not branching

#164 ghost opened 4 years ago
2
risc-v implementation in vivado 2018.2

#163 andrewavram34 opened 4 years ago
1
Fix simpleuart baud rate calculation

#162 anishathalye opened 4 years ago
0
testing

#161 bilkarpooja opened 4 years ago
1
simulation error

#160 bilkarpooja closed 4 years ago
1
simulation error

#159 bilkarpooja closed 4 years ago
2
added default clk divider parameter to simpleuart

#158 rxrbln closed 4 years ago
0
Beginner Question- more RAM on HX8K

#157 nbelanger99 closed 4 years ago
0
fix readme icebreaker links

#156 dehann closed 4 years ago
0
Request for an example that tiggers an interrupt from HDL.

#155 mkvenkit closed 4 years ago
4
Sending optional WREN cmd

#154 nalzok opened 4 years ago
0
Beginner question: understanding the SB_IO primitive

#153 nalzok closed 2 years ago
1
Fix #151 (missing irqs)

#152 RolinBert closed 4 years ago
0
Sporadically missing IRQs which last only one clock cycle (e.g. timer irq)

#151 RolinBert closed 4 years ago
0
Integrating with OSS-Fuzz

#150 Google-Autofuzz closed 4 years ago
0
undefined reference to `memcpy'

#149 JunnanLi closed 4 years ago
2
Workarround: Disable cmd_memtest() when starting firmware.

#148 splinedrive closed 4 years ago
2
port linux and picorv32 on fpga

#147 winner96 opened 4 years ago
6
Added printf and use it thruout the firmware.

#146 rxrbln opened 4 years ago
0
spimemio documentation: read latency reset value

#145 Novakov closed 4 years ago
0
Regarding source code

#144 ghanesimit opened 4 years ago
1
picovr32 picosoc hx8demo, static and global vars have weird values!

#143 splinedrive opened 4 years ago
1
picorv32_pcpi_div register reset

#142 smurray798 closed 4 years ago
4
added CROSS prefix and CFLAGS to the picsoc/Makefile

#141 rxrbln closed 4 years ago
2
UART Baud rate error

#140 RobPearce opened 4 years ago
1
picorv32 on VC707

#139 salmansheikh closed 4 years ago
2
Short modification in the error string

#138 pcotret closed 4 years ago
0
Debug interface

#137 MarekPikula opened 4 years ago
0
Tiny issue in firmware help :)

#136 ghost closed 5 years ago
0
Incorrect simulation of always block with commercial simulators

#135 chiraag closed 5 years ago
2
mem_addr output becomes xxxxxxxx

#134 XIVN1987 closed 5 years ago
0
picorv32_pcpi_div: Signed divide error (R): 00000001 % 800ab000: sw = ffffffff, hw = 00000001

#133 XIVN1987 closed 5 years ago
2
iverilog simulate error: jump to wrong address, and decode instruction at wrong address

#132 XIVN1987 closed 5 years ago
4
Add tracing support to dhrystone test

#131 tomverbeure closed 5 years ago
0
Consider providing Prerequisites section for PicoSoC

#130 kuzminrobin opened 5 years ago
2
README typo(s).

#129 kuzminrobin closed 5 years ago
1
lots of warnings

#128 FrankBuss closed 5 years ago
0
How do I implement irq handling in soc_ecp5_evn?

#127 minecraft2048 closed 5 years ago
1
Performance

#126 drtrigon closed 5 years ago
4
What MMU would you recommend with this?

#125 WarlockD closed 5 years ago
1
How to handle section .eh_frame in linker script

#124 drtrigon closed 5 years ago
4
RISC-V JTAG Implementation

#123 mongsim closed 5 years ago
1
fix firmware/sections.lds section size alignment on 4 bytes

#122 yanghao closed 5 years ago
2
Bug: function call

#121 drtrigon closed 5 years ago
4
Can you upload the max frequency that picorv32 could run on Xilinx Atrix-7?

#120 hyf6661669 closed 5 years ago
2
Equivalent Gate Count PicoRV32I

#119 apdn closed 5 years ago
2
RISC-V tests

#118 aignacio closed 5 years ago
1

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