ZipCPU wb2axip issues - Githubissues

ZipCPU / wb2axip

Bus bridges and other odds and ends

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AXILUPSZ has the wrong shift for WSTRB

#62 ZipCPU opened 9 months ago
0
variable 'M_AXIS_TDATA' should not be used in output port connection axivfifo.v":792

#61 ivansun1688 opened 10 months ago
1
wbxbar slave-side STB remains asserted beyond ACK for one clock cycle for single word transaction.

#60 epsilon537 closed 11 months ago
10
fusesoc file based on CAPI 1 standard.

#59 johnathan-convertino-afrl opened 11 months ago
2
something went wrong (I guess : the version of tools)

#58 xlxwzybds closed 1 year ago
1
the patreon support

#57 xlxwzybds closed 1 year ago
2
Arbitration Behaviour of axixbar

#56 predator2k closed 1 year ago
4
Why does the axixclk module has no wid input/output?

#55 predator2k closed 1 year ago
2
is the axiclk can be used in the axi lite scenario

#54 yuanjin0928 closed 1 year ago
4
axisafety.v in ZYNQ Ultrascale+ works for read operations, but not for write operations

#53 madorskya closed 1 year ago
11
axim2wbsp.v: has different data endianness for write and read channels

#52 abyszuk closed 2 years ago
1
Whether the situation crossing 4K boundary has been handled in AXIDMA？

#51 zhoulikeda closed 2 years ago
2
Question regarding AW / W channel dependencies

#50 tristanitschner closed 2 years ago
8
Missing LICENSE file

#49 hughperkins closed 2 years ago
3
File 'faxi_valaddr.v' is missing

#48 jiegec closed 2 years ago
1
Is the OPT_NONESEL option currently the same as the multiple slaves?

#47 aylons opened 2 years ago
1
Enhacement: Sync only on TLAST option for axis2mm

#46 baileyji closed 2 years ago
10
`default_nettype none breaks vivado global synthesis

#45 baileyji closed 2 years ago
10
Possible enhancement: add AWCACHE parameter to axis2mm

#44 baileyji closed 2 years ago
2
Vivado Block design, local param, and axixbar

#43 baileyji closed 2 years ago
2
Kicking off a transfer with AXIS2MM

#42 baileyji closed 2 years ago
16
AXIS2MM & WUSER bits/byte causes critical warning in Vivado

#41 baileyji closed 2 years ago
3
Eliminate Ports S_AXI_C* Until Supported by AutoFPGA

#40 bobnewgard closed 3 years ago
4
Fix formal properties of skidbuffer

#39 Alkaid-Benetnash closed 3 years ago
1
axi2axilite

#38 forflo closed 3 years ago
3
skid buffer proved by smtbmc but fail by abc pdr

#37 jimmysitu closed 3 years ago
3
AXIS2MM FIX: address and length reads while busy

#36 ZipCPU closed 3 years ago
0
`s2mm` doesn't update address or len external registers

#35 archshift closed 3 years ago
2
Which yosys version should I use?

#34 jimmysitu closed 3 years ago
2
Icarus-verilog elaboration failed in axixbar.v

#33 jiegec closed 3 years ago
1
axi2wb: Fix invalid sel value when reading

#32 t123yh closed 3 years ago
1
illegal localparam in list of parameters

#31 speq closed 3 years ago
2
Syntax error in axidma.v

#30 jiegec closed 3 years ago
1
axisafety module fails tests with ZYNQ + AXI BRAM controller

#29 madorskya closed 4 years ago
7
restore default nettype to wire

#28 akukulanski closed 4 years ago
3
always block with constant assignment

#27 eschmidscs closed 3 years ago
3
Interfacing to Xilinx Vivado block design environment

#26 motylewski opened 4 years ago
8
aximwr2wbsp increments address too early, first data written to the next incremented address

#25 motylewski closed 4 years ago
4
axi2axilite missing DW on axi_addr instances

#24 saberhawk closed 4 years ago
1
missing src/spec.tex

#23 tcmichals closed 4 years ago
3
Missing doc file lgpl-3.0.pdf?

#22 tcmichals closed 4 years ago
2
Wrong AXI-Stream port names in aximm2s.v

#21 rlee287 closed 4 years ago
1
aximm2s didn't compile for data busses > 32b

#20 bogdanvuk closed 4 years ago
1
Regarding err_state in WB to AXI 4 Lite Bridge

#19 Nishikant-github closed 4 years ago
4
Vivado block design changes

#18 ZipCPU closed 4 years ago
2
Fix empty statement in sequential block warning

#17 d953i closed 4 years ago
4
High throughput AXI full master.

#16 d953i closed 4 years ago
1
xlnxdemo formal verification fails

#15 bluewww closed 5 years ago
3
Added default nettype wire to the end of each file

#14 ZipCPU closed 5 years ago
0
`default_nettype none causes issues when integrating with Xilinx IP

#13 bchetwynd closed 5 years ago
5