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aignacio
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ravenoc
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
MIT License
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Issue 20
#22
aignacio
closed
4 days ago
0
Does the router use a pipeline structure?
#21
Alexander-0619
opened
1 month ago
8
question about test_irqs
#20
sfyhhh
opened
1 month ago
4
questions about regression test
#19
sfyhhh
closed
2 months ago
3
Regarding Head, Body and Tail Flits
#18
kutaybulun
closed
3 months ago
1
FPGA Implementation Multiple Driver Error
#17
kutaybulun
closed
3 months ago
4
Implementation on an FPGA
#16
kutaybulun
closed
4 months ago
1
How to use this repo
#15
Rohit123451
closed
11 months ago
1
regarding the configurable files
#14
Siddhanth09
closed
11 months ago
4
Add ack pulse irq
#13
aignacio
closed
1 year ago
0
Mult burst pkt support
#12
aignacio
closed
1 year ago
0
Wr buffer full
#11
aignacio
closed
1 year ago
0
Design of flit fifo of RaveNoC Router using Block RAM for area optimization in FPGA platform
#10
madhumita-mukherjee
closed
1 year ago
14
router top file：Confused about ns_con
#9
Elena32061
closed
2 years ago
2
what does *N-*FIFO mean here?
#8
Elena32061
closed
2 years ago
3
Why is IRQ needed？
#7
Elena32061
closed
2 years ago
2
Why the project only has axi slave interface
#6
Elena32061
closed
2 years ago
1
What is the meaning of “ def_wr_dec, def_rd_dec ” in ”axi slave if“ file
#5
Elena32061
closed
2 years ago
3
Unable to run regression tests
#4
kevinpinto98
closed
2 years ago
7
What is the interpretation of names `axi_mosi_if` and `axi_miso_if`
#3
hughperkins
closed
2 years ago
2
Nit: missing a space in license paragraph
#2
hughperkins
closed
2 years ago
1
Verification
#1
EngRaff92
opened
3 years ago
1