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amacgillivray
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rv32_core
KU EECS 581 / 582 senior design project. This is project an attempt to study / explore CPU implementations, with an original goal of implementing the RISCV "V" extension. Code currently incomplete.
MIT License
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What pins should IO ports be mapped to?
#108
amacgillivray
opened
1 year ago
0
Synthesizable core in RE branch
#107
amacgillivray
closed
1 year ago
0
Fix basic syntax errors caught in vivado
#106
amacgillivray
closed
1 year ago
0
Bring main up to date
#105
amacgillivray
closed
1 year ago
0
Finish defs file and fix all references
#104
amacgillivray
closed
1 year ago
0
Pull sprint 8 end
#103
amacgillivray
closed
1 year ago
0
Vector Instruction Set - Reference
#101
amacgillivray
closed
1 year ago
0
Test the reverse-engineered RV32IM core with Zedboard in Vivado &/or verify it with riscv-dv and exactstep
#99
amacgillivray
opened
1 year ago
0
rewrite regfile.v
#98
amacgillivray
closed
1 year ago
0
write pipe_ctrl.v
#97
amacgillivray
closed
1 year ago
0
write multiplier.v
#96
amacgillivray
closed
1 year ago
0
write mmu.v
#95
amacgillivray
closed
1 year ago
0
write lsu.v
#94
amacgillivray
closed
1 year ago
0
write issue.v
#93
amacgillivray
closed
1 year ago
0
write fetch.v
#92
amacgillivray
closed
1 year ago
0
write exec.v
#91
amacgillivray
closed
1 year ago
0
write divider.v
#90
amacgillivray
closed
1 year ago
0
write decode.v / decoder.v
#89
amacgillivray
closed
1 year ago
0
write csr_regfile.v
#88
amacgillivray
closed
1 year ago
0
write csr.v
#87
amacgillivray
closed
1 year ago
0
Write core.v
#86
amacgillivray
closed
1 year ago
0
Write defs file
#85
amacgillivray
closed
1 year ago
0
Rewrite ALU
#84
amacgillivray
closed
1 year ago
0
Ultra Embedded RISCV Reference
#82
AditiDarade
closed
1 year ago
0
Work on profiling real-world use-cases
#81
amacgillivray
closed
1 year ago
0
Write a small test program and compile to assembly
#80
amacgillivray
closed
1 year ago
0
Functionality for RV32IM
#79
amacgillivray
closed
1 year ago
0
fixed id_mux1
#78
Andal01
closed
2 years ago
0
Clean repository and remove deprecated code
#77
amacgillivray
closed
2 years ago
0
Fix ID MUX 1
#76
amacgillivray
closed
2 years ago
0
Bring latest into main
#75
amacgillivray
closed
2 years ago
0
Bring Jarrod's changes into cores branch
#74
amacgillivray
closed
2 years ago
1
IF/ID Latch
#73
amacgillivray
closed
2 years ago
0
Instruction Memory
#72
amacgillivray
closed
2 years ago
0
Adder for PC
#71
amacgillivray
closed
2 years ago
0
PC Register
#70
amacgillivray
closed
2 years ago
0
Adder for IF Mux
#69
amacgillivray
closed
2 years ago
0
Instruction Fetch Mux
#68
amacgillivray
closed
2 years ago
0
Fixes #49
#66
Daniel-Gins
closed
2 years ago
0
Update readme.md
#65
alexarcher721
closed
2 years ago
0
Add files via upload
#64
AditiDarade
closed
2 years ago
0
Remove .d files and .gitignore them
#63
amacgillivray
closed
2 years ago
0
Merge fixes
#62
amacgillivray
closed
2 years ago
0
Remove .d files from the repository and add to .gitignore
#61
amacgillivray
closed
2 years ago
0
Pull ALU into main
#59
amacgillivray
closed
2 years ago
0
[Master Issue] - Components of RISC-V Core
#58
amacgillivray
opened
2 years ago
1
#47 - Replace vector with Queue
#57
Daniel-Gins
closed
2 years ago
1
Implement Copy, Move constructors on Request class
#52
amacgillivray
closed
2 years ago
0
Req. #18 - Create diagrams of system
#51
amacgillivray
closed
2 years ago
1
Req. #17 - Determine how inputs to user programs should be handled?
#50
amacgillivray
closed
2 years ago
0
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