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aws
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aws-fpga
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
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AWS XVC question
#602
jimmy-adams
closed
1 year ago
2
Change DEVICE to PLATFORM
#601
hgminh95
opened
1 year ago
0
Will there be future support for 2022.x (and 2021.2) tool versions in AL2 AMIs?
#600
abejgonzalez
opened
1 year ago
2
update README (#735)
#599
kyyalama2
closed
1 year ago
0
test
#598
oops408
closed
1 year ago
0
Hi,
#597
Gogul-N
closed
1 year ago
2
PCIS interface AXI ID
#596
abhaywindsor
closed
1 year ago
2
Changing A1 frequency
#595
abhaywindsor
closed
1 year ago
3
How were the IPs in hdk/common/shell_v04261818/design created without any project
#594
za1nrkhan
closed
1 year ago
3
cl_hello_world_ref_hx fails to synthesis
#593
johnrabo
closed
1 year ago
7
MSI-X interrupts from CL are not supported when using SHELL without XDMA?
#592
ehudeliaz
closed
1 year ago
3
Update dpi_xsim.tcl for cl_hello_world_ref_hlx example
#591
johnrabo
opened
1 year ago
0
Unable to simulate hello world HLx in vivado
#590
johnrabo
closed
1 year ago
3
Bug in PCIM interface model?
#589
nmoroze
opened
1 year ago
3
fix: secondary process crash
#588
pengjianzhang
opened
1 year ago
3
Add all potentially necessary sources for elaborating sh_ddr module
#587
ChrisKjellqvist
closed
1 year ago
0
Building DCP fails when using sh_ddr
#586
ChrisKjellqvist
closed
1 year ago
4
xilinx_aws-vu9p-f1_shell-v04261818_201920_3.xsa file is missing
#585
Temerson0
closed
1 year ago
2
EC2 F1: AWS FPGA DRAM DMA Example fails during execution
#584
jasmisbvb
closed
1 year ago
7
ERROR: [BD 5-336] This command cannot be run, as the BD-design is locked.
#583
svpolonsky
closed
1 year ago
6
trivial update
#582
kyyalama2
closed
1 year ago
0
[Question]: FPGA Peer2Peer Build Process
#581
sajjadahmed677
closed
1 year ago
4
Remove git clean invocation from DRAM model generation
#580
davidbiancolin
closed
1 year ago
6
Xilinx 2022.1
#579
bjourne
closed
1 year ago
19
What is the reason for reset synchronization in new CL design template?
#578
za1nrkhan
closed
1 year ago
1
What is xdma0_user mapped to?
#577
Quarky93
closed
2 years ago
3
Updates to documentation
#576
kyyalama2
closed
2 years ago
0
Does HLX flow still work?
#575
Quarky93
closed
2 years ago
11
Unable to run FPGA dev AMI on r6 and c6 instances
#574
kenta2
closed
2 years ago
3
Example cl_hello_world_ref_hlx fails in newer Vivado versions
#573
wirthjohannes
closed
1 year ago
6
Using-PCIe-Write-Combining example returns unexpected results
#572
itamarblum
opened
2 years ago
3
Unable to run FPGA dev AMI on m6a or m6i instances
#571
kenta2
closed
2 years ago
6
XOCL installation failed.
#570
Shahzaib2028
closed
2 years ago
2
Fixed the cl_uram_example Constraints
#569
kyyalama2
closed
2 years ago
0
Update wait_for_afi.md
#568
kyyalama2
closed
2 years ago
0
fix broken links in the RTL_sim doc (#715)
#567
kyyalama2
closed
2 years ago
0
pnr updates for uram fix
#566
kyyalama2
closed
2 years ago
0
[Quesstion]: Simulation of virtual jtag facility
#565
sajjadahmed677
closed
2 years ago
7
non-default device IDs and udev rules
#564
jacobmgn
closed
2 years ago
0
Updates to documentation for migration between F1 and U200 in vivado flow
#563
kyyalama2
closed
2 years ago
0
Updates to documentation for migration between F1 and U200 in vivado flow
#562
kyyalama2
closed
2 years ago
0
fixes #560: udev rule not running after loading fpga image
#561
cmoore1776
closed
2 years ago
1
udev rule not running after loading fpga image
#560
cmoore1776
opened
2 years ago
6
prepare_new_cl.sh generates broken scripts and templates.
#559
jahagirdar
opened
2 years ago
4
Notify scripts gives boto3.exception
#558
jahagirdar
closed
1 year ago
6
Vivado Fails to Synthesize Anything Other Than the Example Projects Using the Build Scripts
#557
llee454
closed
2 years ago
8
AXI "bvalid" behavior and latency
#556
useragdp1
closed
2 years ago
3
Some image URLs are broken in documentation
#555
whentojump
closed
2 years ago
3
[Question]: DDR Burst Read
#554
sajjadahmed677
closed
2 years ago
4
peer2peer DMA
#553
useragdp1
closed
2 years ago
2
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