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byuccl
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iprec
Xilinx CoreGen module recognition project. Lead author Corey Simpson.
Apache License 2.0
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make templates.json output to lib dir
#22
reillymck
closed
1 year ago
0
Updated README to reflect new project structure
#21
KeenanRileyFaulkner
closed
1 year ago
0
Changed ip to be positional argument, always first
#20
KeenanRileyFaulkner
closed
1 year ago
0
make ip argument positional and first
#19
KeenanRileyFaulkner
closed
1 year ago
0
Split json and dcp files into their own directories
#18
KeenanRileyFaulkner
closed
1 year ago
1
Catch failed designs and prevent dcp generation
#17
reillymck
opened
1 year ago
0
Reilly refactor
#16
reillymck
closed
1 year ago
1
Invalid IP configurations are generated
#15
reillymck
opened
1 year ago
1
Clean up vivado subprocess on kill of script
#14
jgoeders
opened
1 year ago
0
fixing more path issues, also adding architecture document
#13
dallinjdahl
closed
1 year ago
0
fixing path bugs
#12
dallinjdahl
closed
1 year ago
0
Parallel
#11
dallinjdahl
closed
1 year ago
0
Unittest
#10
reillymck
closed
1 year ago
4
allowing tcl commands to be written to streams instead of only files.
#9
dallinjdahl
closed
1 year ago
0
Adjust code to fix syntax bug
#8
reillymck
closed
1 year ago
4
Vivado ip fix
#7
reillymck
closed
1 year ago
1
adding logging to search_lib.py and eliminating useless if statements
#6
dallinjdahl
closed
1 year ago
0
Refactor progress
#5
reillymck
closed
1 year ago
0
adding logging to search_lib.py
#4
dallinjdahl
opened
1 year ago
0
adding unit test runner
#3
dallinjdahl
closed
1 year ago
0
Add license file
#2
nelsobe
closed
2 years ago
0
Create LICENSE
#1
nelsobe
closed
2 years ago
0