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chipsalliance
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aib-protocols
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update ca_align_mux.v
#96
nij-intel
closed
1 year ago
1
channel align per-channel strobe detection logic is not reset correctly for SYNC_FIFO=0
#95
nij-intel
closed
1 year ago
1
Update CA user guide tx/rx online signal block diagram
#94
saravi1x
closed
3 months ago
0
update axi full examples with correct rx_buffer size
#93
nij-intel
closed
1 year ago
1
AXI4-ST drops TREADY when traffic is started before AIB link up
#92
nij-intel
closed
2 years ago
3
AXI4-ST asymmetric design examples should use user strobe only
#91
nij-intel
closed
2 years ago
2
AXI and LPIF tests need to use latest AIB 2.0 RTL
#90
dkehlet
closed
2 years ago
2
make run in axi4-st/full_examples/sims/tb_mf2.1_sh1_d256 failed
#89
xinyang2k
closed
2 years ago
5
Double-flop synchronize data from SPI SCLK domain to AVMM clock
#88
dkehlet
closed
2 years ago
1
Free-running SPI Clock
#87
kbradley09
closed
2 years ago
2
Duplicate state assignment in reset block
#86
kbradley09
closed
2 years ago
1
Change reset value of SPI follower miso to 1
#85
dkehlet
closed
2 years ago
1
[1.0] AXI Streaming test failure
#84
nij-intel
closed
2 years ago
4
[1.0] CA run_nightly.sh error
#83
nij-intel
closed
2 years ago
4
directed reset test not toggling tx_online
#82
nij-intel
closed
2 years ago
5
axi4-mm addr width cover point not correct
#81
nij-intel
closed
2 years ago
4
[0.9.7] CA test_M2S2_GEN2_F2F_18 fails
#80
nij-intel
closed
2 years ago
2
CA not able to generate coverage report
#79
nij-intel
closed
2 years ago
2
AXIMM synthesis not optimizing unused pipeline registers
#78
nij-intel
closed
3 months ago
1
CA DV randomize number of channels for testing
#77
nij-intel
closed
2 years ago
4
CA VPD dump support
#76
nij-intel
closed
2 years ago
2
[0.9.6] CA M2S2_GEN2F2F_18 and M2S2_GEN2_F2F_ALIGN_FLY1_1 test fails
#75
nij-intel
closed
2 years ago
4
[0.9.6] CA M2S2_GEN2_F2F_23 test fails
#74
nij-intel
closed
2 years ago
5
[0.9.6] CA M2S2_GEN2_F2F_22 test fails
#73
nij-intel
closed
2 years ago
10
[0.9.6] CA smoke test clean up needed
#72
nij-intel
closed
2 years ago
1
CA scripts clean up
#71
nij-intel
closed
2 years ago
2
[0.9.6] CA DV align error: M2S2_GEN2_F2F_13
#70
nij-intel
closed
2 years ago
6
CA DV: BAD case in is_stb_beat above beat
#69
nij-intel
closed
2 years ago
2
[LPIF] x1, Gen 1 configurations
#68
arta-eximiusdesign
closed
2 years ago
4
CA regression runs only ca_basic_test
#67
nij-intel
closed
2 years ago
3
CA DV scoreboard issue
#66
nij-intel
closed
2 years ago
1
[LPIF] Regression script is broken in 0.9.5
#65
mjwEE
closed
2 years ago
2
LPIF question on pipeline behavior
#64
johna-eximiusdesign
closed
2 years ago
3
pl negotiation matrix
#63
johna-eximiusdesign
closed
2 years ago
4
Question on PTM_RX_DELAY parameter
#62
johna-eximiusdesign
closed
2 years ago
4
CA and LPIF regression and coverage document
#61
nij-intel
closed
2 years ago
3
Chiplet SPI User Guide bug: Table 1
#60
dkehlet
closed
2 years ago
1
AXILITE bready timeout
#59
nij-intel
closed
2 years ago
2
AXI4-MM regression failures
#58
nij-intel
closed
2 years ago
12
AXI4 coverage exclusion for tx_online and rx_online
#57
nij-intel
closed
2 years ago
3
AXI4 warnings clean up
#56
nij-intel
closed
2 years ago
4
Needs example design DV for all individual IPs. (No UVM env)
#55
xinyang2k
closed
2 years ago
1
AXI4 regression and coverage document
#54
nij-intel
closed
2 years ago
2
single channel expecting channel skew in configuration
#53
nij-intel
closed
2 years ago
2
spi-aib: Add chiplet user status and chiplet user control registers to the SPI follower
#52
dkehlet
closed
2 years ago
2
Doc issues
#51
dkehlet
closed
2 years ago
1
spi-aib: please update SPI_User_Guide.pptx
#50
dkehlet
closed
2 years ago
1
master/slave align_done in phy_to_aib.sv
#49
nij-intel
closed
2 years ago
5
[LPIF] Handshaking Protocol type from device to host adaptor
#48
mjwEE
closed
2 years ago
8
AXI4-Stream UVM_ERROR in scoreboard: uvm_test_top.axist_scb [axist_scoreboard] Transmit tdata size 15
#47
nij-intel
closed
3 years ago
3
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