furrtek DMG-CPU-Inside issues

furrtek / DMG-CPU-Inside

Reverse-engineered schematics for DMG-CPU-B

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issues

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KOTA and JAFA are AND gates

#83 msinger opened 2 years ago
0
HUDA is an AND

#82 msinger opened 2 years ago
0
GOJY is connected to wrong output of EMER

#81 msinger opened 2 years ago
0
ETAN is a NOR

#80 msinger opened 2 years ago
0
Misleading notes/labels on page 20 (APU CH4)

#79 msinger opened 2 years ago
0
HYNO is AND

#78 msinger opened 2 years ago
0
APU CH1 and CH2 volume envelope only work when AOI_MUX_2 cells have output inverted

#77 msinger opened 2 years ago
2
Rare type of single-output flip-flop may have Q instead of !Q

#76 msinger opened 2 years ago
0
HAFE is a NOR gate

#75 msinger opened 2 years ago
0
BYHO has wrong input

#74 msinger opened 2 years ago
0
DOXA is a NOR gate

#73 msinger opened 2 years ago
0
KAKE in an OR gate

#72 msinger opened 2 years ago
0
KYNY and KYLY are two names for the same cell

#71 msinger opened 2 years ago
0
Reset of registers FF24 and FF25 is wrong

#70 msinger opened 2 years ago
0
BUDA needs inverted CPU_RD

#69 msinger opened 2 years ago
0
Wrong input 4 for CUGU

#68 msinger opened 2 years ago
0
XECY is wrong flip-flop type

#67 msinger opened 2 years ago
0
GAXU is an AND, not a NAND

#66 msinger opened 2 years ago
0
Clock inputs of FF25 register need to be inverted one more time

#65 msinger opened 2 years ago
2
Adders EFYK and EJOK got wrong input

#64 msinger opened 2 years ago
0
CH3_REGS and CHANNEL3 errors (schematic side)

#63 jbshelton opened 2 years ago
1
FERY inverts FF18, not DUCE

#62 msinger opened 2 years ago
1
FAPE is a NAND

#61 msinger opened 2 years ago
0
RUTE should be getting RACU instead of RACO

#60 msinger opened 2 years ago
0
Simple output buffers are inverting

#59 msinger opened 2 years ago
0
AWOD is a NOR gate

#58 msinger opened 2 years ago
0
Data lines of OAM and it's CPU RD is active-low/inverted

#57 msinger opened 2 years ago
0
The bigger tri-state buffers are all non-inverting

#56 msinger opened 2 years ago
0
All input buffers are inverting

#55 msinger opened 2 years ago
1
T1 and T2 have inverting input buffers

#54 msinger opened 2 years ago
0
MEGU doesn't actually have a !Q output

#53 msinger opened 3 years ago
1
AVOK gets wrong output of ATYK

#52 msinger opened 3 years ago
0
Input 1 of NAXY is wrong

#51 msinger opened 3 years ago
0
Unlabeled CPU clock inputs

#50 msinger opened 3 years ago
0
SYRO also connects to CPU

#49 msinger opened 3 years ago
0
Input 2 of TEGU is wrong

#48 msinger opened 3 years ago
0
Label FROM_CPU5 is wrong; it's going TO the CPU

#47 msinger opened 3 years ago
0
Label FROM_CPU is wrong; should be !T1_T2

#46 msinger opened 3 years ago
0
CPU_WR_RAW going into REFA is actually just CPU_WR

#45 msinger opened 3 years ago
0
LYXE wrongly connected to LORU

#44 msinger opened 3 years ago
1
AFER gets clocked by BOGA

#43 msinger opened 3 years ago
0
First input of GEDO is wrong

#42 msinger opened 3 years ago
0
Output of ATOK is missing a label that indicates where it is going

#41 msinger opened 3 years ago
0
FALU should be connected to !Q output of GAPO

#40 msinger opened 3 years ago
0
TAME, TOMA

#39 rgalland opened 3 years ago
0
TOBU Q

#38 rgalland opened 3 years ago
0
Labels KUTU, KUPE, KUNU, (...) should reflect being driven by !Q output of FFs

#37 msinger opened 3 years ago
0
FEVO should be connected to Q output of GUXE, and FUVO to !Q

#36 msinger opened 3 years ago
0
KYVO should be connected to COUT of JORE

#35 msinger opened 3 years ago
0
The "audio output" of channel 2 is not labelled

#34 msinger opened 3 years ago
0