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jkiv
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shapool-core
FPGA core for SHA256d mining targeting Lattice iCE40 devices.
BSD 3-Clause "New" or "Revised" License
20
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7
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Cool! - Can we know what is the speed?
#25
akshar001
closed
3 years ago
7
Update for icepool 2021-02
#24
jkiv
opened
3 years ago
0
Integrate CI
#23
jkiv
opened
3 years ago
0
Update `pinout-ice40up5k-b-evn.pcf` to reflect new signal scheme
#22
jkiv
closed
3 years ago
1
Update `pinout-ice40hx8k-b-evn.pcf` to reflect new signal scheme
#21
jkiv
closed
3 years ago
1
Pinouts and make targets should be board-specific
#20
jkiv
closed
3 years ago
0
Make test bench names consistent
#19
jkiv
closed
3 years ago
0
Specify difficulty at build time
#18
jkiv
closed
3 years ago
4
Separate Makefile, Code for tests
#17
jkiv
closed
3 years ago
0
Update Makefile for next-pnr
#16
jkiv
closed
3 years ago
1
External IO as separate module
#15
jkiv
closed
3 years ago
1
Active low global reset
#14
jkiv
closed
3 years ago
0
Proper State Machines
#13
jkiv
closed
3 years ago
3
Alternate interface to COPI1/CIPO1
#12
jkiv
closed
3 years ago
1
Tests using `libftdi`
#11
jkiv
closed
3 years ago
1
Makefile default: print message about building
#10
jkiv
opened
4 years ago
0
Update signal names MISO, MOSI, GMISO, and GMOSI
#9
jkiv
closed
3 years ago
2
Update README to reflect behaviour, parameters, and SPI interface.
#8
jkiv
closed
3 years ago
2
Finalize SPI mode
#7
jkiv
closed
3 years ago
2
Formal verification
#6
jkiv
opened
4 years ago
1
Add support for ECP5
#5
jkiv
opened
4 years ago
3
Use Block RAM for input/output shift registers on ice40.
#4
jkiv
opened
5 years ago
4
yosys fails to parse sha_unit.v
#3
jkiv
closed
5 years ago
1
Test device using prototyping MCU.
#2
jkiv
closed
3 years ago
2
Update pinout to reflect icepool-board.
#1
jkiv
closed
3 years ago
7