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jotego
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jtopl
Verilog module compatible with Yamaha OPL chips
GNU General Public License v3.0
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Y8950 implementation
#15
retrofan1979
closed
2 months ago
1
Fix jt2413.qip
#14
gyurco
closed
7 months ago
0
Bad assignments
#13
jotego
closed
8 months ago
2
Pass OPL_TYPE to jtopl_csr
#12
gyurco
closed
2 years ago
0
Volume issue in MiSTer cores
#11
mills32
closed
8 months ago
7
Add qip files to target/quartus (#9)
#10
gyurco
closed
2 years ago
1
Please restore the .qip files
#9
gyurco
closed
2 years ago
12
jtopl.f missing
#8
bit-hack
closed
2 years ago
2
Different fix for the timer
#7
gyurco
closed
2 years ago
7
drum sounds weird in OPL3 chip
#6
suww37
closed
2 years ago
1
Fix timer irq activation 1 period earlier
#5
gyurco
closed
2 years ago
2
Timer immediately overflows when 0xff is loaded into it
#4
gyurco
closed
2 years ago
5
Wrong sounds
#3
gyurco
closed
2 years ago
8
Bad Dudes ending theme
#2
jotego
closed
2 years ago
2
Set dout to a zero byte if read mode is not asserted
#1
nullobject
closed
4 years ago
2