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`VerilogTranslationPass` fail with the following example.
```
def mk_aType(a: int = 4, b: int = 6):
return mk_bitstruct(
"aType",
{
"a": mk_bits(a),
…
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Xyce/ADMS recognises three display system tasks:
`$strobe` displays when the simulator has converged on a solution for all nodes;
`$display` provides the same capabilities as `$strobe`;
`$write` …
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`yosys> plugin -i systemverilog
ERROR: Can't load module `./systemverilog': /usr/bin/../share/yosys/plugins/systemverilog.so: undefined symbol: _ZN5Yosys4Pass11on_registerEv`
ubuntu 20.04 LTS in W…
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Hello.
hdlConvertor does not support the parallel_case attribute. An example can be found here: https://github.com/KatCe/hdlConvertor_issue_185
Using the python script in the repo I tried all 3…
KatCe updated
10 months ago
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While we don't know about good open-source linters for VHDL and SpinalHDL, **(System)Verilog** has got at least three: **Verilator**, **Verible**, **Slang**. Check [this](https://github.com/chili-chip…
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Opening Settings -> Editor -> Code style -> System Verilog hangs forever. This means you can't edit the coding style at the moment.
igmar updated
5 years ago
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**Description**
When using the GHDL plugin to yosys, and probably more generally, attributes are not attached to instantiations. This causes (for example) yosys to optimise away instantiated blocks …
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I get the same error when trying to generate the bitstream from the command line. Furthermore, to open the design in Vivado, I don't know which files to include.
**Command:** make CONFIG=rocket64b2 …
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where can I find the verilog versions of the ztachip as Iam not familiar with the VHDL
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Hi Vitor,
Many thanks for your excellent work on this plugin! I was trying it, and saw that sv structs and class still can't do autocompletion. I saw issue #150 is still open and got to wonder if t…