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### Describe the bug
For the special case where synthesis netlists preserve hierarchy and OpenROAD flattens them, the resulting naming convention in the netlist and that of the SPEF file do not appea…
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Dear Bruno,
my congratulations for squeezing a RV32I core into the Icestick !
I read your Verilog files with joy and I wish to share an idea on how to save a few more LUTs for more peripherals: …
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The test generation flow appears broken when I try to customize the default target rv64gc with PMP support for SV39 mode on Mentor or Cadence simulators?
I've pulled in upstreams upto `d74484b -…
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I'm trying to get started with cocotb following the [quickstart guide](https://docs.cocotb.org/en/stable/quickstart.html). I cloned the repo and navigated to `examples/doc_examples/quickstart/` wh…
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It would be good to generate docker containers which support multiple architectures. As things seem to already be using `buildx` / `buildkit` style builds, it might be as simple as following the instr…
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Halide has started failing to build recently. This is probably due to a change in configuration on my part, since it also affects old tags that used to build. However the issue seems to be limited to …
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### Subject
ORFS failed at global placement stage
[Stage]: Global Placement.
### Describe the bug
[NesterovSolve] Iter: 310 overflow: 0.813046 HPWL: 5619862180
Command terminated by signal 11…
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Some FPGAs feature internal temperature sensors.
It would be great to integrate these in LiteX and access them in Linux to read out the current operating temperature of the chip.
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Hi, @jerryz123 we were corresponding about this project over email before.
I've run my RVV benchmark on it again, and there are still a few benchmarks that run into bugs.
The results for the wor…
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This is a very nice example and can be used as a reference for pyuvm. I can see by the coding style that System Verilog UVM influences it. It would be nice to incorporate some of the good practices fr…