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Hello,
I just started with Gemmini and Chipyard and not I am facing some issues with the Softmax, GELU and LayerNorm activation functions.
I got Gemmini running and I get the correct results for …
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### Is there an existing CVA6 task for this?
- [X] I have searched the existing task issues
### Task Description
I have a private fork of the cva6 project in which I have added hardware and softwar…
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Can you help me with the compile flags for VexiiRiscv to generate a system with cache-coherent TL ports? The default seems to build a "cacheless config".
In general, what are the best set of flags …
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Hi, I am working on the physical ASIC implementation of this IP. I am integrating this IP into a new chip and I am having issue with the xilinx dual ports dual clock memories instantiated into dualmem…
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**Description**
Tool doesn't recognize the work library.
**Expected behaviour**
Design file imports packages from work library, and while the files are included in the .sby file (im using symbiyo…
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**What is your question?**
DISCLAIMER: This is a question and suggestion. let me know if you want me to seperate the suggestion into a seperate issue for tracking my feature request.
I actively us…
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[Enter steps to reproduce:]
1. Open project
2. Open project file
**Atom**: 1.17.0-beta2 x64
**Electron**: 1.3.14
**OS**: Mac OS X 10.12.4
**Thrown From**: Atom Core
### Stack Trace
U…
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By looking at the sources of this repo, it seems that the project is to generate artifacts for a wide range of platforms (both OSs and architectures). That's nice! However, I'm lacking some explanatio…
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Yesterday I decided to try using an Interface.
I am currently experimenting with a StructType object to mimic the VHDL _record_ / SystemVerilog _struct_, and wanted to get a feel for the 'how and wha…
josyb updated
7 years ago
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## **Describe the bug** - _A clear and concise description of what the bug is_.
There appears to be a problem with the way this extension works with the vscode config parser.
In that, unlike other…