-
Here is what error report said:
```
cd $HOME/verilator-optimization/rocket-chip && mill emulator[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.DefaultConfig].mfccompiler.compil…
-
This issue tracks the remaining subissues that must be fixed before UVM can be converted to C++. This first comment is updated periodically to summarize the most recent state.
**Note UVM is not ye…
-
This is with a custom `maxOtherSize` (I set it to 10% instead of 5%). Maybe this is the cause?
-
```scala
class MyBundle extends Bundle{
val a,b = UInt(8 bits)
// or : val a = UInt(8 bits)
// val b = UInt(8 bits)
}
object Play2 extends App{
import spinal.core.sim._
SimConf…
-
### Issue
When using the build option YICES_STUB=1 during building in order to disable Yices, BSC fails to build with error
```
/build/bluespec-git/src/bsc/inst/bin/bsc -stdlib-names -bdir /build…
-
I'm simulating the single-core rocket-chip (https://github.com/OpenXiangShan/rocket-chip/tree/dev-difftest). I observe quite different simulation performance on this design with the latest version of …
-
I am a beginner working with rocket chip generator for my project but I am not able to generate the verilog file for it and facing this error. I am using an apple M1 chip macOS. I started with cloning…
-
The VivadoSynth tool located in `bfasst/tools/synth/vivado_synth.py` is sufficient for doing what the VivadoSynthFromTcl tool is doing. If you compare the following two files, you will see they are es…
-
Please see the issue here that's raised on the rocketchip's github page:
https://github.com/chipsalliance/rocket-chip/issues/3483
Current upstream RocketChip has moved to using Mill instead of SBT…
-
Handshake has ready/valid semantics. ESI has valid/ready semantics. Let's marry them.