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SOFA
SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
https://skywater-openfpga.readthedocs.io/en/latest/
MIT License
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Fixed IO register pb_type map
#96
mkurc-ant
closed
3 years ago
1
Fix parsing error in FPGA1212_QLSOFA arch file.
#95
WRansohoff
closed
3 years ago
0
Commented out shift_register mode in k4_N8 VPR architecture.
#94
mkurc-ant
closed
3 years ago
1
using default yosys script instead of custom script for multi_enc_dec…
#93
sharmaln
closed
3 years ago
1
Models and pb_types annotation for k4_N8 VPR architecture
#92
mkurc-ant
closed
3 years ago
2
(1)CFG_DONE to add is_config_enable(2)reset default=1 under tile_anno…
#91
liaokevin-ql
closed
3 years ago
5
SOFA branch ql_ccff_dummy_stdcell_pointer
#90
liaokevin-ql
closed
3 years ago
1
Using custom yosys script for benchmarks run in generate_testbench task
#89
sharmaln
closed
3 years ago
0
Minor fix on the waveform display for I/O circuitry
#88
tangxifan
closed
3 years ago
0
add 4 global clocks
#87
tpagarani
closed
3 years ago
0
Merging registered/non-registered related IO definition in k4_N8 device
#86
sharmaln
closed
3 years ago
3
Replacing deprecated tile_port syntax
#85
sharmaln
closed
3 years ago
1
Update task conf
#84
sharmaln
closed
3 years ago
0
Adding interface definition for registered IOs
#83
sharmaln
closed
3 years ago
1
Updating conf file to run custom yosys script on a benchmark design
#82
sharmaln
closed
3 years ago
1
QL specific architecture compatible with AP3
#81
tpagarani
closed
3 years ago
7
Physical design - Critical patch on dangling nets in logic elements
#80
ganeshgore
closed
3 years ago
0
Critical patch on dangling nets in logic elements
#79
tangxifan
closed
3 years ago
0
Update documentation with latest GDS view
#78
tangxifan
closed
3 years ago
0
Updated GDS with chip art + Cleanup
#77
ganeshgore
closed
3 years ago
0
Caravel Testbench for And2_latch benchmark
#76
tangxifan
closed
3 years ago
0
General updates to pass MPW precheker
#75
ganeshgore
closed
3 years ago
0
Testbenches for Caravel + FPGA integration
#74
tangxifan
closed
3 years ago
0
Updated SOFA-CHD - Updated cells - DRC Clean
#73
ganeshgore
closed
3 years ago
0
Minor updates to SOFA-HD and QLSOFA-HD to fix LVS test
#72
ganeshgore
closed
3 years ago
4
Rename testbench to be consistent with post-PnR netlist path changes
#71
tangxifan
closed
3 years ago
0
Updated SOFA-HD and QLSOFA-HD to meet caravel boundary requirement
#70
ganeshgore
closed
3 years ago
2
Update on post-pnr verification files for CHD version
#69
tangxifan
closed
3 years ago
0
Update sphinx bibtex version requirement to avoid icompatible versions
#68
tangxifan
closed
3 years ago
0
Updated CHD design with mux_primitive fix
#67
ganeshgore
closed
3 years ago
0
FPGA I/O cell Update
#66
tangxifan
closed
3 years ago
0
Bug fix in the custom cell code generator
#65
tangxifan
closed
3 years ago
0
Release of Testbenches for SOFA CHD version and Documentation Update
#64
tangxifan
closed
3 years ago
0
Fine-tune architecture file to be consistent in port naming of SOFA CHD
#63
tangxifan
closed
3 years ago
0
Bug fix on the CI dependency for OpenFPGA-run in Github Actions
#62
tangxifan
closed
3 years ago
0
SOFA CHD Post-PnR Netlist
#61
tangxifan
closed
3 years ago
0
Scripts to Automate the Synthesis for the decoders in FPGAs with custom cells
#60
tangxifan
closed
3 years ago
0
Now modelsim verification is multithreaded
#59
tangxifan
closed
3 years ago
2
Scripts for Verifications on Custom Cell -based FPGA (SOFA CHD)
#58
tangxifan
closed
3 years ago
0
Added Caravel merge and precheck in action + Updated SOFA-HD and QLSOFA-HD gds
#57
ganeshgore
closed
3 years ago
0
Python script to adapt OpenFPGA netlist to use custom MUX cells
#56
tangxifan
closed
3 years ago
0
Major Changes in Documentation
#55
tangxifan
closed
3 years ago
0
Critical Patches on Simulation Scripts and Testbenches
#54
tangxifan
closed
3 years ago
0
Make github action builds path aware
#53
ganeshgore
opened
3 years ago
0
Ganesh dev
#52
ganeshgore
closed
3 years ago
0
Add new architecture files which use custom cells based on Skywater HD library
#51
tangxifan
closed
3 years ago
0
Add wrapper generator examples to CI
#50
tangxifan
closed
3 years ago
0
Increase routing chan width from 40 to 60 for the architecture using reset and soft adders
#49
tangxifan
closed
3 years ago
0
Add Continuous Integration
#48
tangxifan
closed
3 years ago
0
Bug fix in the arch port naming
#47
tangxifan
closed
3 years ago
2
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