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SOFA
SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
https://skywater-openfpga.readthedocs.io/en/latest/
MIT License
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Cannot run with newest version of OpenFPGA
#147
franktaTian
closed
5 months ago
6
SOFA HD has no reset, how it affects FPGA's performance?
#146
WazaAbdulkadir
opened
1 year ago
1
Overlapping macro layouts
#145
mbaykenar
closed
1 year ago
3
LEF file for pregenerated eFPGAs
#144
LYWalker
opened
1 year ago
4
Timing report details
#143
msaideroglu
closed
1 year ago
2
How did you harden tiles?
#141
WazaAbdulkadir
closed
1 year ago
3
Instructions for synthesis and PnR for SOFA?
#140
gussmith23
opened
1 year ago
7
the post-layour areas
#139
narutozxp
opened
2 years ago
0
Scripts for PnR
#138
yunuseryilmaz18
opened
2 years ago
0
FPGA1212_QLSOFA_HD_task reproducing fabric netlists
#137
ghost
closed
2 years ago
4
SOFA timing analysis with sdc file input does not give timing report
#136
ghost
closed
2 years ago
0
Unknown `write_verilog_testbench` command in the OpenFPGA flow
#135
romangauchi
closed
2 years ago
1
Fix typos causing the unknown `write_verilog_testbench` command errors
#134
romangauchi
closed
2 years ago
2
Git repo mismatch while installing caravel. Issue with open_pdks
#133
nandithaec
opened
2 years ago
1
Some question
#132
kangliyu1
opened
2 years ago
2
some questions about QLSOFA_HD_PNR
#131
kangliyu1
opened
3 years ago
0
is skywater130 pdk supported by synopsys
#130
ghost
closed
2 years ago
8
Failed to execute openfpga flow
#129
ghost
closed
3 years ago
5
How do we change the standard cell library being used here?
#128
iamkarthikbk
opened
3 years ago
1
VPR fails to PnR
#127
abdullahyildiz
opened
3 years ago
0
Functional Simulaton of SOFA RTL Design
#126
abdullahyildiz
closed
3 years ago
2
Update generate_testbench.openfpga
#125
tangxifan
closed
3 years ago
0
write_verilog_testbench is not defined in latest OpenFPGA release
#124
abdullahyildiz
closed
3 years ago
6
Update openfpga shell script due to the deprecation of 'write_verilog_testbench'
#123
tangxifan
closed
3 years ago
0
Add SOFA+ Architecture with fracturable 18x18 multiplier
#122
tangxifan
closed
3 years ago
3
[Demo] Runs only counter example
#121
ganeshgore
closed
3 years ago
0
[CICD] Force CI on the master push/after merge to master
#120
ganeshgore
closed
3 years ago
0
[Repo] Adding Skywater PDK as a submodule
#119
ganeshgore
closed
3 years ago
0
[Flow] Updated CHD design
#118
ganeshgore
closed
3 years ago
0
[Flow] QLSOFA Updated flow and ARCH
#117
ganeshgore
closed
3 years ago
0
[Cleanup] Dropped old build.yml
#116
ganeshgore
closed
3 years ago
2
[Cleanup] Dropping base 2x2 design
#115
ganeshgore
closed
3 years ago
0
Update conf.py
#114
tangxifan
closed
3 years ago
0
Figure and hyperlink updates for Custom Cells Documentation
#113
GrantBrown1994
closed
3 years ago
0
Update README.md with links to documentation
#112
tangxifan
closed
3 years ago
0
[CICD] Adding docker based regression test
#111
ganeshgore
closed
3 years ago
0
[Flow] Adding makefile for running task
#110
ganeshgore
closed
3 years ago
0
Update timing annotation for SOFA CHD
#109
tangxifan
closed
3 years ago
0
Adding custom cell lib file for timing analysis
#108
ganeshgore
closed
3 years ago
0
Update timing annotation
#107
tangxifan
closed
3 years ago
0
Add bitstream generation flow-run
#106
tangxifan
closed
3 years ago
0
Documentation Updates
#105
tangxifan
closed
3 years ago
0
Custom cell documentation added
#104
GrantBrown1994
closed
3 years ago
4
Add report timing scripts
#103
tangxifan
closed
3 years ago
1
CPL custom cell documenation
#102
GrantBrown1994
closed
3 years ago
0
Fix the mismatched name of Quicklogic's yosys scripts in task configuration files
#101
tangxifan
closed
3 years ago
0
Added arch exploration files
#100
apond308
closed
3 years ago
1
Response to OpenFPGA PR #231: SOFA XMLs updated with new frac_lut4_arith arch
#99
liaokevin-ql
closed
3 years ago
0
Fix spelling of floorplan.
#98
mithro
closed
3 years ago
0
ICC2 scripts?
#97
nachiket
opened
3 years ago
2
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