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pulp-platform
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chimera
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JTAG EoC Procedure
#54
Lore0599
opened
1 hour ago
0
[TB]: Extend testbench to improve debugging
#53
Lore0599
closed
1 hour ago
1
Lleone/fix datawidthmismatch
#52
Lore0599
closed
1 week ago
0
Bump Cheshire dependencies to revert AXI version
#51
Lore0599
closed
1 week ago
1
[HW]: Add axi cut in the memory island domain to remove timing loops
#50
Lore0599
closed
2 weeks ago
1
PR: Bump ETH & KUL dependencies
#49
Scheremo
closed
1 week ago
0
[HW]: Bugs Fix
#48
Lore0599
closed
4 weeks ago
0
Integrate Hyperbus peripheral
#47
sermazz
closed
1 day ago
4
Reintroduced SelectCfg parameter
#46
Lore0599
closed
1 month ago
0
Lleone/cfg param
#45
Lore0599
closed
1 month ago
0
Reorganize chimera_pkg
#44
sermazz
closed
1 month ago
0
add config registers to hyperbus
#43
arpansur
closed
15 hours ago
1
CVA6 PLEN fix
#42
Scheremo
closed
1 month ago
2
lleone/memisland
#41
Lore0599
closed
1 month ago
0
Lleone/pmu
#40
Lore0599
closed
1 month ago
0
UPF Cluster AXI Structured Ports
#39
Lore0599
closed
1 month ago
0
APB interface
#38
Lore0599
closed
2 months ago
0
Add clock gate peripherals
#37
Lore0599
closed
2 months ago
0
add kul sw test function
#36
xiaoling-yi
opened
2 months ago
2
hw: Make external register mapping + naming more explicit
#35
Scheremo
closed
2 months ago
0
Add include guards to header files
#34
Scheremo
closed
2 months ago
0
ASIC Target
#33
Lore0599
closed
2 months ago
0
Integrate Hyperbus peripheral
#32
Scheremo
closed
1 month ago
0
Integrate `narrow_adapter` into `chimera_cluster_adapter`
#30
micprog
opened
2 months ago
0
HW: Rename registers to align nomenclature
#29
Scheremo
closed
2 months ago
1
Improve makefile flow
#28
sermazz
closed
2 months ago
2
Revert Commit #69cc1bc
#27
Scheremo
closed
2 months ago
0
Align RISCV Debug Module
#25
Lore0599
closed
2 months ago
2
HW: Refactor Cluster integration
#24
Scheremo
closed
2 months ago
0
Add support for 32 AXI Data & Address width
#23
Scheremo
closed
2 months ago
1
Add formatting to CI linting rules
#22
Scheremo
closed
2 months ago
0
Bump Cheshire dependency
#21
Scheremo
closed
2 months ago
5
Lleone/fix interrupt
#20
Lore0599
closed
3 months ago
0
CI: Support test case insertion into nonfree repo
#19
Scheremo
closed
3 months ago
1
Make the CI slightly happer
#18
Scheremo
closed
3 months ago
2
Update Bender.lock to reflect updated memory island dependency
#17
Scheremo
closed
3 months ago
4
Move internal CI manifest to nonfree
#16
sermazz
closed
3 months ago
2
Add support for multiple parallel functional regression test
#15
Scheremo
closed
3 months ago
0
Implement basic CI flow
#14
sermazz
closed
3 months ago
0
Bypass wide memory register
#13
Lore0599
closed
3 months ago
0
Fixup typos in soc_addr_map.h
#12
Scheremo
closed
3 months ago
0
PR: Fix offloading and returning from Snitch Cluster(s)
#11
Scheremo
closed
3 months ago
0
Create the chip top module
#10
adimauro-iis
closed
3 months ago
0
Cleaner/clearer simulation flow
#9
FrancescoConti
opened
3 months ago
2
iDMA version alignment.
#8
yvantor
closed
3 months ago
2
Create the Verilated model
#7
adimauro-iis
opened
3 months ago
0
Create the emulator target
#6
adimauro-iis
opened
3 months ago
0
Verification setup
#5
adimauro-iis
opened
3 months ago
0
Create the FPGA target
#4
adimauro-iis
opened
3 months ago
0
Integrate new IPs in the Chimera SoC template
#3
adimauro-iis
opened
3 months ago
0
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