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pulp-platform
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common_cells
Common SystemVerilog components
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[test] internal PR
#179
niwis
closed
1 year ago
0
ci: Skip gitlab-ci on forks
#178
niwis
closed
1 year ago
0
Fix HideStrb feature of mem_to_banks
#177
micprog
closed
1 year ago
0
oops wrong button ^^'
#176
ourspalois
closed
1 year ago
0
Recent change in verilator broke stuff (or at least that's my understanding of it)
#175
ourspalois
opened
1 year ago
0
Trivial FIFO TB additions
#174
bluewww
closed
1 year ago
0
feature/idea: using a multiplexer to iterate between new and old values in clk_int_div
#173
oops408
opened
1 year ago
0
Clock divider configuration fails if divider value is 0
#172
fimtrey
closed
1 year ago
0
Allow clock divider configuration while clock is disabled
#171
meggiman
closed
1 year ago
1
Add shift_register_gated
#170
qian-gu
closed
1 year ago
1
A gated shift register module
#169
qian-gu
closed
1 year ago
2
registers: Update load-enable FF macros
#168
stmach
closed
1 year ago
0
Add priority encoder
#167
emanueleparisi
closed
1 year ago
3
fix ifdef verilator
#166
davideschiavone
closed
1 year ago
0
add more ifdef verilator
#165
davideschiavone
closed
1 year ago
1
update assertions for sv2v+yosys
#164
davideschiavone
closed
1 year ago
3
Add glitch free clock multiplexer
#163
meggiman
closed
1 year ago
1
fall_through_register: Remove superfluous `$size` call to allow the use of union types in DCnxt 2022.03
#162
thommythomaso
closed
1 year ago
0
mem_to_banks: Move from axi to common_cells
#161
thommythomaso
closed
1 year ago
0
`stream_fifo_optimal_wrap`: Remove assertions
#160
fischeti
closed
1 year ago
1
fix(fusesoc): add missing header file in `common_cells.core` (#158)
#159
qian-gu
closed
1 year ago
0
missing assertions.svh in common_cells.core
#158
qian-gu
closed
1 year ago
1
add dummy assign
#157
davideschiavone
closed
1 year ago
4
Module Name Overlap with Xilinx Internal
#156
christian-lanius
opened
1 year ago
0
Update `fall_through_register`'s fifo to `fifo_v3`
#155
michael-platzer
closed
1 year ago
1
Update CI and fix lint
#154
micprog
closed
2 years ago
0
Allow out-of-bounds top end address in addr_map
#153
micprog
closed
2 years ago
0
stream_throttle: Add a module that restricts the number of outstanding transfers in a stream
#152
thommythomaso
closed
2 years ago
0
Add stream_join_dynamic IP
#151
colluca
closed
11 months ago
4
Stream join dynamic IP with independent input handshakes
#150
colluca
closed
11 months ago
0
cb_filter: Add Vivado IPX compatibility
#149
niwis
opened
2 years ago
0
Exclude `cb_filter` from Vivado IP packager projects
#148
paulsc96
closed
2 years ago
0
Use glitch-free `tc_clk_mux` muxes in `rstgen_bypass`
#147
paulsc96
closed
2 years ago
0
Remove `program` blocks from testbenches for VCS compatibility
#146
paulsc96
closed
2 years ago
0
`id_queue`: Add support for multidimensional arrays
#145
niwis
opened
2 years ago
1
Add `addr_decode_napot`
#144
paulsc96
closed
2 years ago
1
Fix FuseSoc core version
#143
hossein1387
closed
2 years ago
0
stream_fifo_wrap: Add a wrapper that optimally selects either a spill register or a fifo
#142
thommythomaso
closed
2 years ago
1
update fusesoc manifest file
#141
davideschiavone
closed
2 years ago
0
stream_register: Replace FIFO with FFs
#140
stmach
closed
2 years ago
1
add support for fusesoc and vivado xsim
#139
skokvermon
closed
2 years ago
2
Fix toolproblems in `id_queue`
#138
SamuelRiedel
closed
2 years ago
0
Align src_files.yml with Bender
#137
glaserf
closed
2 years ago
0
Small typofix for clk div in src_files.yml
#136
glaserf
closed
2 years ago
0
Bender.yml: Fix file name error
#135
micprog
closed
2 years ago
0
Wrong filename in `Bender.yml`
#134
paulsc96
closed
2 years ago
0
lzc: Add assertion for parameters
#133
SamuelRiedel
closed
2 years ago
2
Configurable arbitrary integer clock divider
#132
meggiman
closed
2 years ago
1
Add optional seed parameter to stream_delay module
#131
meggiman
closed
2 years ago
0
Edge propagator ack
#130
glaserf
closed
2 years ago
2
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