rust-embedded riscv issues

rust-embedded / riscv

Low level access to RISC-V processors

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issues

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Fix linker file for RISCV-64 targets

#236 romancardenas opened 7 hours ago
2
riscv: define medeleg using CSR macros

#235 rmsyn closed 20 hours ago
2
riscv: use CSR macros for mcounteren

#234 rmsyn opened 4 days ago
0
riscv: define mcause using CSR macros

#233 rmsyn closed 2 days ago
1
riscv: define marchid using CSR macros

#232 rmsyn closed 6 days ago
0
riscv: re-use `mcountinhibit` `try_*` functions

#231 rmsyn closed 4 days ago
1
Update critical-section to 1.2.0

#230 romancardenas closed 1 week ago
0
riscv: redefine CSR registers with new helper macros

#229 rmsyn opened 1 week ago
4
Prepare for new release

#228 romancardenas closed 1 week ago
0
Make support for u-boot

#227 mekosko closed 2 months ago
26
`riscv`: Advanced Interrupt Architecture support

#226 bjorn3 opened 2 months ago
0
riscv: fix mtvec address field

#225 rmsyn closed 2 months ago
1
riscv-semihosting: fix ambiguous documentation link

#224 00xc closed 2 months ago
0
Support for non-standard exception and interrupts (clean)

#223 romancardenas closed 1 week ago
27
riscv: add fallible functions

#222 rmsyn closed 3 months ago
14
riscv-rt-macros: update syn to v2.0

#221 agarof closed 4 months ago
5
mstatus: Support vector extension

#220 jasonwhite closed 4 months ago
0
riscv: add CSR-defining macros

#219 rmsyn closed 1 week ago
18
`riscv`: Add macro to define CSR register types

#218 rmsyn closed 1 week ago
5
riscv: add `mcounteren` in-memory update functions

#217 rmsyn closed 5 months ago
1
Fix semihosting::debug::exit() on riscv64 QEMU targets.

#216 kevin-vigor closed 5 months ago
0
Fix semihosting::exit() on riscv64 QEMU targets.

#215 kevin-vigor closed 5 months ago
2
fixup: riscv: fix `mstatus` test

#214 rmsyn closed 5 months ago
0
riscv: add `mcountinhibit` module

#213 rmsyn closed 5 months ago
2
`riscv`: Consider strategy for exception safe code

#212 rmsyn closed 3 months ago
8
Support "non-standard" interrupts and exceptions

#211 romancardenas closed 3 months ago
16
Align jump targets to 4 bytes

#210 hegza closed 5 months ago
1
`riscv`: All the CSR write operations should be unsafe by default

#209 jsgf opened 5 months ago
3
Tidy per-ext check-cfg flags

#208 jsgf closed 5 months ago
2
Add Mstatus helpers to allow setting fields in Mstatus

#207 jsgf closed 5 months ago
10
Implement Eq and PartialEq for Range and Permission

#206 jsgf closed 5 months ago
1
riscv: build: make `cfg` variables more robust

#205 rmsyn closed 5 months ago
5
`riscv`: register: fix target architecture conditional compilation

#204 rmsyn closed 5 months ago
12
`riscv`: register: exports macros for custom CSRs

#203 rmsyn closed 6 months ago
0
`riscv-rt`: link.x expected filename pattern

#202 roby2014 closed 6 months ago
1
Add Mstatus::from(usize)

#201 jasonwhite closed 6 months ago
0
`riscv-rt`: Support for vectored mode interrupt handling

#200 romancardenas closed 5 months ago
9
`riscv-rt`: make `abort` weak

#199 romancardenas closed 7 months ago
0
Add some utility methods to Mstatus and Mcause

#198 dreiss closed 7 months ago
2
`riscv-rt`: Duplicate symbol when linking with Newlib

#197 gmmyung closed 7 months ago
1
`riscv-rt`: Broken eh_frame relocations on QEMU

#196 dreiss opened 7 months ago
4
`riscv-peripheral`: Support Core-Local Interrupt Controller (CLIC) RISC-V Privileged Architecture Extensions

#195 hegza closed 5 months ago
6
Fix mistake in changelog

#194 Property404 closed 7 months ago
0
`riscv`: Support more fence variants

#193 jsgf opened 7 months ago
1
`riscv-rt`: Machine + Supervisor mixed executable

#192 ZhekaS opened 7 months ago
1
Fix sip::{set,clear}_ssoft

#191 Property404 closed 7 months ago
0
`riscv-rt`: `_pre_init_trap` and weak symbols

#190 romancardenas closed 7 months ago
0
`riscv-rt`: Assembly algorithm for RAM init incompatible with upcoming RVE extension (future proofing)

#189 hegza opened 8 months ago
1
`riscv-rt`: add `pre_init_trap` handler to detect errors during the boot process

#188 romancardenas closed 7 months ago
1
`riscv`: Pub macros for non-standard CSRs

#187 dreiss closed 6 months ago
1