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rust-embedded
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riscv
Low level access to RISC-V processors
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Publish latest riscv-rt patch on crates.io
#177
romancardenas
closed
7 months ago
0
Avoid spurious errors from LLVM
#176
romancardenas
closed
7 months ago
1
`riscv-rt`: LLVM raises spurious errors in release mode for instructions of ISA extensions (e.g., M or E)
#175
daniestevez
opened
7 months ago
5
Release new versions
#174
romancardenas
closed
7 months ago
2
Release time
#173
romancardenas
closed
7 months ago
2
lib: update dependency embedded-hal to 1.0.0
#172
jakezhu9
closed
7 months ago
2
`riscv-semihosting`: bug fixes
#171
romancardenas
closed
7 months ago
0
add `riscv-semihosting`
#170
romancardenas
closed
7 months ago
2
`riscv`: ECALL and nested interrupts
#169
romancardenas
closed
8 months ago
1
`riscv-rt`: add links to Cargo.toml
#168
romancardenas
closed
7 months ago
0
`riscv-rt`: clean linker script
#167
romancardenas
closed
8 months ago
0
`riscv-rt`: Implement FPU initialization
#166
mini-ninja-64
closed
8 months ago
2
`riscv`: support for S-mode
#165
romancardenas
closed
8 months ago
1
Add `riscv-peripheral` crate
#164
romancardenas
closed
6 months ago
3
`riscv`: support for S-mode
#163
romancardenas
closed
8 months ago
0
riscv-pac crate
#162
romancardenas
closed
8 months ago
1
`riscv-rt`: Rework on exception and interrupt handling
#161
romancardenas
closed
8 months ago
0
`riscv-rt`: remove riscv-target ;`riscv`:update for embedded-hal to 1.0.0-rc.2
#160
romancardenas
closed
8 months ago
1
Update for embedded-hal to 1.0.0-rc.2
#159
purplethunder
closed
8 months ago
7
Add riscv-rt to workspace
#151
romancardenas
closed
9 months ago
2
Transition to cargo workspace
#150
romancardenas
closed
9 months ago
2
Remove FCSR
#149
romancardenas
closed
9 months ago
0
FCSR operations generally cannot be used from Rust
#148
RalfJung
closed
9 months ago
2
Update embedded-hal to 1.0
#147
romancardenas
closed
10 months ago
0
RFC: Platform-specific exception codes
#146
SoulSharer
opened
10 months ago
2
Add CI for CHANGELOG.md file
#145
romancardenas
closed
10 months ago
0
remove peripheral module
#144
romancardenas
closed
10 months ago
2
Removing user mode registers
#143
romancardenas
closed
10 months ago
6
Rework on misa and mstatus
#142
romancardenas
closed
11 months ago
0
asm: set unsafety of `nop` and `delay` functions to safe
#141
luojia65
closed
11 months ago
0
Remove bit_field dependency
#140
romancardenas
closed
11 months ago
3
Rework of mcause and scause registers
#139
romancardenas
closed
1 year ago
0
scause: add missing LoadMisaligned
#138
orangecms
closed
1 year ago
2
Sync with master
#137
romancardenas
closed
1 year ago
0
Skip [] in docs
#136
romancardenas
closed
1 year ago
0
ACLINT and CLINT peripherals
#135
romancardenas
closed
10 months ago
6
Remove bors
#134
romancardenas
closed
1 year ago
5
Replace bors with GitHub merge queues
#133
romancardenas
closed
1 year ago
2
Update GitHub workflows
#132
romancardenas
closed
1 year ago
10
fix a typo
#131
OccupyMars2025
closed
1 year ago
2
`sip` register set / clear functions
#130
PitiBouchon
closed
1 year ago
4
PLIC peripheral
#129
romancardenas
closed
1 year ago
6
Add FENCE instruction
#128
rmsyn
closed
1 year ago
3
Add FENCE.I instruction
#127
rmsyn
closed
1 year ago
4
lib: gate delay module and asm under `delay` feature
#126
luojia65
closed
11 months ago
2
Generic PLIC peripheral
#125
romancardenas
closed
1 year ago
12
`riscv-peripheral`: add standard peripherals
#124
romancardenas
opened
1 year ago
12
Added clippy to the CI workflow
#123
romancardenas
closed
1 year ago
3
`riscv-rt`: Can you have two versions in the build tree at the same time?
#152
TheButlah
closed
7 months ago
1
release v0.10.1 with critical section bug
#122
almindor
closed
1 year ago
2
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