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rust-embedded
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riscv
Low level access to RISC-V processors
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PLIC peripheral
#129
romancardenas
closed
1 year ago
6
Add FENCE instruction
#128
rmsyn
closed
1 year ago
3
Add FENCE.I instruction
#127
rmsyn
closed
1 year ago
4
lib: gate delay module and asm under `delay` feature
#126
luojia65
closed
1 year ago
2
Generic PLIC peripheral
#125
romancardenas
closed
1 year ago
12
`riscv-peripheral`: add standard peripherals
#124
romancardenas
opened
1 year ago
12
Added clippy to the CI workflow
#123
romancardenas
closed
1 year ago
3
`riscv-rt`: Can you have two versions in the build tree at the same time?
#152
TheButlah
closed
9 months ago
1
release v0.10.1 with critical section bug
#122
almindor
closed
1 year ago
2
fix critial section implementation
#121
tfx2001
closed
1 year ago
3
`riscv-rt`: Linker relocation issue (QEMU / OpenSBI)
#153
chutchinson
opened
1 year ago
6
`riscv-rt`: Using this as a library?
#154
hyperswine
closed
8 months ago
5
release v0.10.0
#120
almindor
closed
1 year ago
2
create a release for the atomicity things
#119
orangecms
closed
1 year ago
1
tag the 0.9.0 release
#118
orangecms
closed
1 year ago
1
fix atomicity of critical section, fixes #116
#117
almindor
closed
2 years ago
10
The `critical_section` implementation is wrong
#116
Tnze
closed
2 years ago
3
Why are bare-metal and embedded-hal dependencies of this crate?
#115
romancardenas
closed
2 years ago
1
`riscv`: `interrupt::free()` for Supervisor Mode
#114
FawazTirmizi
closed
10 months ago
1
bump version to v0.9.0 due to breaking changes
#113
almindor
closed
2 years ago
1
Propose to release a version `riscv` v0.8.1
#112
luojia65
closed
2 years ago
9
Fix `interrupt::free()` unsoundness on multicore systems.
#111
Dirbaio
closed
2 years ago
1
Add critical-section 1.0 implementation, fix multicore unsoundness.
#110
Dirbaio
closed
2 years ago
11
Update to edition 2021.
#109
Dirbaio
closed
2 years ago
1
fix: clearify that mip.{MSIP, MTIP} are read-only
#108
luojia65
closed
2 years ago
2
fix reading marchid and mimpid
#107
orangecms
closed
2 years ago
3
Add embedded-hal v1.0.0-alpha.8 support
#106
almindor
closed
1 year ago
4
Add extra documentation for `delay`
#105
Joeyh021
closed
2 years ago
3
Fix asm::delay not clobbering count register
#104
adamgreig
closed
2 years ago
4
Fix release year in changelog
#103
Disasm
closed
2 years ago
2
Prepare v0.8.0 release
#102
Disasm
closed
2 years ago
2
Fix changelog
#101
Disasm
closed
2 years ago
4
Support for riscv32imc.
#100
mgaggero
closed
2 years ago
6
Remove uses of unstable features and always use inline assembly
#99
taiki-e
closed
2 years ago
3
Add builders for registers
#98
jwnhy
closed
1 month ago
2
`riscv`: Linking fails when using this crate as a dependency
#97
JarredAllen
closed
5 months ago
5
Update embedded-hal dependency to 1.0.0-alpha.7
#96
ahmedcharles
closed
1 year ago
6
Fix copyright year
#95
Disasm
closed
2 years ago
2
csr: inline register reads and type conversations
#94
luojia65
closed
2 years ago
7
Remove riscv target post fix triple information from asm archive name
#93
MabezDev
closed
2 years ago
3
`riscv-rt`: Prune unused symbols
#155
piegamesde
closed
7 months ago
0
RISCV sdk with RUST support
#92
AchyuthAGNA5675
closed
1 year ago
3
Add inline-asm build to CI, fix build
#91
Disasm
closed
2 years ago
2
add asm::nop, asm::delay, and delay.rs.
#90
dkhayes117
closed
2 years ago
1
Add `asm::nop`, `asm::delay`, and an Mcycle-based delay with Embedded-hal traits
#89
dkhayes117
closed
2 years ago
1
`riscv-rt`: Pre initialization trap handling
#156
piegamesde
closed
7 months ago
2
Bug fix: sfence.vma - incorrect operand order
#88
DeathWish5
closed
2 years ago
2
add singleton macro
#87
gnxlxnxx
closed
2 years ago
3
feat: Use new asm! instead of llvm_asm!
#86
duskmoon314
closed
3 years ago
4
"cannot link object files with different floating-point ABI" rustc 1.56.0-nightly (2021-08-06)
#85
o8vm
closed
3 years ago
2
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