Github: http://github.com/ultraembedded/riscv
A 32-bit RISC-V core written in Verilog and an instruction set simulator supporting RV32IM.
This core has been tested against a co-simulation model and exercised on FPGA.
For a higher performance dual issue CPU with branch prediction, see my latest RISC-V core here; http://github.com/ultraembedded/biriscv
Param Name | Valid Range | Description |
---|---|---|
SUPPORT_SUPER | 1/0 | Enable supervisor / user privilege levels. |
SUPPORT_MMU | 1/0 | Enable basic memory management unit. |
SUPPORT_MULDIV | 1/0 | Enable HW multiply / divide (RV-M). |
SUPPORT_LOAD_BYPASS | 1/0 | Support load result bypass paths. |
SUPPORT_MUL_BYPASS | 1/0 | Support multiply result bypass paths. |
SUPPORT_REGFILE_XILINX | 1/0 | Support Xilinx optimised register file. |
EXTRA_DECODE_STAGE | 1/0 | Extra decode pipe stage for improved timing. |
MEM_CACHE_ADDR_MIN | 32'h0 - 32'hffffffff | Lowest cacheable memory address. |
MEM_CACHE_ADDR_MAX | 32'h0 - 32'hffffffff | Highest cacheable memory address. |
Name | Contents |
---|---|
core/riscv | RISC-V pipelined RV32IM CPU core (Verilog) |
isa_sim | Instruction set simulator (C) |
top_tcm_axi/src_v | Example instance with 64KB DP-RAM & AXI Interfaces |
top_tcm_axi/tb | System-C testbench for the core |
top_cache_axi/src_v | Example instance with instruction and data caches. |
top_cache_axi/tb | System-C testbench for the core |
The top (top_tcm_axi/src_v/riscv_tcm_top.v) contains;
Range | Description |
---|---|
0x0000_0000 - 0x0000_ffff | 64KB TCM Memory |
0x0000_2000 | Boot address (configurable, see RISCV_BOOT_ADDRESS) |
0x8000_0000 - 0xffff_ffff | Peripheral address space (from AXI4-L port) |
Name | Description |
---|---|
clk_i | Clock input |
rst_i | Async reset, active-high. Reset memory / AXI interface. |
rst_cpu_i | Async reset, active-high. Reset CPU core (excluding AXI / memory). |
axit* | AXI4 slave interface for access to 64KB TCM memory. |
axii* | AXI4-Lite master interface for CPU access to peripherals. |
intr_i | Active high interrupt input (for connection external int controller). |
A basic System-C / Verilator based testbench for the core is provided.
Dependencies;
To build the testbench;
cd top_tcm_axi/tb
make
To run the provided test executable;
cd top_tcm_axi/tb
make run
The top (top_cache_axi/src_v/riscv_top.v) contains;
Name | Description |
---|---|
clk_i | Clock input |
rst_i | Async reset, active-high. Reset memory / AXI interface. |
axii* | AXI4 master interface for CPU access to instruction memory. |
axid* | AXI4 master interface for CPU access to data / peripheral memories. |
intr_i | Active high interrupt input (for connection external int controller). |
reset_vector_i | Boot vector. |