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xlsynth
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bedrock-rtl
High quality and composable base RTL libraries in SystemVerilog
Apache License 2.0
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Some bug fixes and refactors for FIFOs
#179
zhemao-openai
closed
6 days ago
0
Enable `BR_ASSERT_STATIC` unconditionally; canonicalize fail strings
#178
mgottscho
closed
1 week ago
0
Don't guard `BR_ASSERT_STATIC` with `BR_ASSERT_ON`
#177
mgottscho
closed
1 week ago
0
FPV: Add FPV enrivornment for arbiters
#176
taoliu-o
closed
1 week ago
0
Use --filelist for all rules
#175
mgottscho
closed
1 week ago
0
Clarify `BR_ENABLE_ASSERT_COMB`
#174
mgottscho
closed
1 week ago
0
Refactor br_flow_arb/br_flow_mux for easier verification
#173
zhemao-openai
closed
1 day ago
1
Make sure push_ready[i] not dependent on push_valid[i] in br_flow_arb libraries
#172
zhemao-openai
closed
1 day ago
1
Remove onehot2bin/bin2onehot encoders in br_arb_rr
#171
zhemao-openai
closed
1 day ago
1
Implement CDC support
#170
zhemao-openai
closed
1 day ago
1
Fix lint issues in `br_ram_addr_decoder`
#169
mgottscho
closed
1 week ago
0
Fix latency asserts in `br_ram_flops_1r1w`
#168
mgottscho
closed
1 week ago
0
Assertion fixes in br_demux_onehot
#167
mgottscho
closed
1 week ago
0
Fix address decoder bugs
#166
mgottscho
closed
1 week ago
0
Fixes to coding style in demuxes to make simulator happier
#165
mgottscho
closed
1 week ago
0
Use `BR_ASSERT_COMB_IMPL` in delay modules
#164
mgottscho
closed
1 week ago
0
New guard: `BR_ENABLE_ASSERT_COMB`
#163
mgottscho
closed
1 week ago
0
Rename SV_ASSERT_ON to BR_ASSERT_ON
#162
mgottscho
closed
1 week ago
0
Comb asserts should pass if expression unknown
#161
mgottscho
closed
1 week ago
0
(dubious) Overhaul broken immediate assertion macros
#160
mgottscho
closed
1 week ago
0
Implement loadable shift register
#159
zhemao-openai
closed
5 days ago
2
Use new fpv and sim wrapper macros; sweep more tests; fix TBs
#158
mgottscho
closed
1 week ago
0
br_tieoff modules do not waive CONST_OUTPUT violation
#157
zhemao-openai
opened
1 week ago
0
New sim and fpv macros
#156
mgottscho
closed
1 week ago
0
Define common test tags for use with `bazel test --test_tag_filters=`
#155
mgottscho
closed
1 week ago
0
Rename `BitWidth` params to `Width`
#154
mgottscho
closed
1 week ago
0
Fix reset bug in `br_delay_valid`
#153
mgottscho
closed
1 week ago
1
Simulation unit test for `br_ram_flops_1r1w`
#152
mgottscho
closed
1 week ago
0
(WIP) chipstack artifacts for br_ram_flops_1r1w
#151
mgottscho
opened
1 week ago
0
Use `br_ram_flops_1r1w` in FIFOs
#150
mgottscho
closed
1 week ago
1
Improve `BR_ASSERT_STATIC` for better logging
#149
mgottscho
closed
1 week ago
0
Lint fail on `br_ram_flops_1r1w` when `EnableMemReset(1)`
#148
mgottscho
opened
1 week ago
0
Implement `br_ram_flops_1r1w`
#147
mgottscho
closed
1 week ago
0
Implement `br_ram_data_rd_pipe`
#146
mgottscho
closed
1 week ago
0
(WIP) `br_ram_addr_decoder_tree`
#145
mgottscho
opened
1 week ago
0
Rename `br_ram_flops_1r1w` to `br_ram_flops_1r1w_tile`
#144
mgottscho
closed
1 week ago
0
Implement demuxes (`br_demux_onehot`, `br_demux_bin`)
#143
mgottscho
closed
1 week ago
0
Implement `br_ram_addr_decoder`
#142
mgottscho
closed
1 week ago
0
Add `br_math_pkg` for non-synthesizable helper functions
#141
mgottscho
closed
1 week ago
0
Add support for non-zero read latency to FIFO controllers
#140
zhemao-openai
closed
1 week ago
0
Overhaul README by documenting all modules, packages, and macros
#139
mgottscho
closed
1 week ago
0
br_mux_bin
#138
mgottscho
closed
1 week ago
0
Merge br_delay_valid_next and br_delay_valid_next_nr into one module with EnableReset parameter
#137
mgottscho
closed
1 week ago
2
RAM tiling and address pipelining
#136
mgottscho
closed
1 week ago
1
(WIP) Tiled and pipelined flop RAM
#135
mgottscho
closed
1 week ago
1
Restore credit available signal to credit counter/receiver/sender and push_credit FIFO
#134
zhemao-openai
closed
2 weeks ago
0
Add output valid signal to onehot2bin module.
#133
mattskl-openai
closed
2 weeks ago
3
Fix br_fifo_flops_push_credit_tb
#132
zhemao-openai
closed
1 week ago
1
Sandbox fixes
#131
mgottscho
closed
2 weeks ago
0
Find way to guarantee that assertion failures cause simulation to exit with nonzero exit code
#130
zhemao-openai
opened
2 weeks ago
0
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