yupferris kaze issues - Githubissues

yupferris / kaze

An HDL embedded in Rust.

Apache License 2.0

194 stars 9 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

Modules with different clock domains?

#40 Boscop closed 1 year ago
3
test trace_test_module_2 failed: panicked at 'assertion failed: `(left == right)`

#39 Boscop opened 1 year ago
1
In-process simulator backend

#38 yupferris opened 2 years ago
0
Additional trace formats

#37 yupferris opened 3 years ago
0
Formal verification support

#36 yupferris opened 3 years ago
0
Add `lsb` and `msb` convenience methods for `Signal`s

#35 yupferris opened 3 years ago
0
Explore async/await for co-sim threads

#34 yupferris opened 3 years ago
0
TraceValue

#33 jdonszelmann opened 3 years ago
0
generate if and else ifs with macros

#32 jdonszelmann closed 3 years ago
1
Add continuous integration

#31 jdonszelmann opened 3 years ago
0
Possible logic errors: Mutable key types

#30 jdonszelmann opened 3 years ago
1
Same name for instances, memories and registers

#29 jdonszelmann opened 3 years ago
0
Same name (the simple cases)

#28 jdonszelmann opened 3 years ago
0
Cannot reproduce: Validation error if a module has no inputs/outputs

#27 jdonszelmann opened 3 years ago
1
Best way to support IP blocks?

#26 MarkSwanson closed 3 years ago
4
Write verilog::generate() output to a file

#25 Uzaaft closed 3 years ago
3
Bit selection of vector signal was missing in generated verilog codes.

#24 ar90n closed 3 years ago
1
Consider redesigning how `Module` (hierarchies) work

#23 yupferris opened 3 years ago
10
Consider multiple clock domains

#22 yupferris opened 3 years ago
0
Tracing improvements

#21 yupferris opened 3 years ago
2
Complete add/sub overloads

#20 yupferris opened 3 years ago
0
Consider growing stacks in compiler instead of iterative lowering

#19 yupferris opened 3 years ago
1
Consider dedicated structure construct

#18 yupferris opened 3 years ago
0
Consider dedicated FSM construct

#17 yupferris opened 3 years ago
0
match/switch construct

#16 yupferris opened 3 years ago
0
Update doc links

#15 yupferris closed 4 years ago
0
Consider writing book/tutorial

#14 yupferris opened 4 years ago
6
Lift signal bit widths into type system when Rust achieves proper support for const generics

#13 yupferris opened 4 years ago
3
Finalize `if` syntax sugar

#12 yupferris opened 4 years ago
0
Non-Recursive Verilog Generator

#11 gkelly closed 3 years ago
2
Document major language assumptions/constraints in high-level docs

#10 yupferris opened 4 years ago
0
Document error detection/handling philosophy

#9 yupferris opened 4 years ago
3
Document typical use cases

#8 yupferris opened 4 years ago
0
Consider higher-level abstractions for signed/unsigned signals

#7 yupferris opened 4 years ago
0
Allow signed values for `Constant`

#6 yupferris opened 4 years ago
0
Come up with random initialization solution for generated sim modules

#5 yupferris opened 4 years ago
0
Come up with tracing solution for generated sim modules

#4 yupferris closed 4 years ago
0
Don't derive `Default` trait to help generate module initialization code

#3 yupferris closed 4 years ago
0
LLHD as Kaze backend

#2 0x7CFE opened 4 years ago
1
Initial bootstrap/TODO

#1 yupferris opened 4 years ago
0