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Siglent SDS1x0xX-E FPGA bitstreams
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Add Hardware Trigger.
#16
enjoy-digital
opened
3 years ago
0
Sim: Allow full flow simulation with Pattern and GLScopeClient.
#15
enjoy-digital
closed
3 years ago
1
Sim: Add Pattern Generator
#14
enjoy-digital
closed
3 years ago
1
Downsampling: Support HAD1511 Dual Mode.
#13
enjoy-digital
opened
3 years ago
0
Use HAD1511 polarity inversion?
#12
enjoy-digital
opened
3 years ago
0
Allow capturing the 4 channels simultaneously.
#11
enjoy-digital
closed
3 years ago
1
Add support for the rotary buttons.
#10
enjoy-digital
opened
3 years ago
1
Add support for second ADC and for Single/Dual/Quad mode.
#9
enjoy-digital
closed
3 years ago
6
Add Auto-Setup script.
#8
enjoy-digital
opened
3 years ago
2
Allow Frontend/VGA/gains configuration.
#7
enjoy-digital
closed
3 years ago
1
Check data ordering in DRAM.
#6
enjoy-digital
opened
3 years ago
2
Allow sampling clock configuration.
#5
enjoy-digital
opened
3 years ago
2
Finish DMA UDP upload.
#4
enjoy-digital
closed
3 years ago
1
Add ADC saturation detection.
#3
enjoy-digital
closed
3 years ago
1
Allow the CPU to initialize DRAM without call to litex_term bridge.
#2
enjoy-digital
closed
3 years ago
1
Add overflow detection on ADC's source to be sure the DRAM can keep up.
#1
enjoy-digital
closed
3 years ago
1