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Hey Yuli,
I am gonna use this project through ASIC Design Approach, Do you have any Tips for me?
Like Did you decide the Clock frequency?, Did you have any cloudy logic that take more than one C…
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https://github.com/Nitheeshkumar521/asic-design-class/blob/main/asiclab1image.jpeg
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# Description
You can use OpenLane2 to convert your Verilog file to a GDSII Layout file. You can refer to [this](https://openlane2.readthedocs.io/en/latest/)
# Notes:
- You are eligible to get br…
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### Feature Description
I'm interested in running designs through sc using standard commercial ASIC tools (in title).
## Steps Taken
* I did a few `grep -R` text searches on the repo looking…
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Hi all,
What are the minimum requirements of a SERV core to design a many-core ASIC using ASAP7 predictive PDK? I'm thinking about something like SMP architecture and I'm going to use [OpenSoC Fabric…
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It would be useful to have table of the different models.
Currently it's quite confusing if you're unfamiliar with the project. E.g. this repo shows the bitaxeUltra as the most recent version, wher…
Sjors updated
2 weeks ago
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Right now I am trying to port the core to a specific ASIC technology. Unfortunately, inferring RAM is ASIC world is not as easy as in FPGA world, so I need to replace all (larger) memory arrays by spe…
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Hi,
I have read your recent journal but cannot really understand the step to do the GL test and get the output render frames. I am quite novice in the ASIC workflow.
To be able to do this test woul…
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where can I find the verilog versions of the ztachip as Iam not familiar with the VHDL
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