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**Goals**:
Required debugging:
- Debug test stand and understand Thursday's results
- [x] Understand where the 600pF on dnn_out come from (measure with ASIC board alone then with ASIC board and c…
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Hey Yuli,
I am gonna use this project through ASIC Design Approach, Do you have any Tips for me?
Like Did you decide the Clock frequency?, Did you have any cloudy logic that take more than one C…
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Thank you very much for such comprehensive information about U25.
I was thinking about getting U25 for myself, but I would like to be sure that SFP+ are connected directly to FPGA, not to the NIC A…
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I noticed a lot buffers are used for driving FrameData and FrameStrobe. I am wondering that the synthesis tools will automatically add buffers, why do we add them in .v file?
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#### Description
Here's a bunch of info:
https://support.edge-core.com/hc/en-us/articles/900000200743--Enterprise-SONiC-Switch-Port-Attributes
```console
admin@leaf1:~$ sudo config interface s…
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Hello,
Thanks for Dashy this is a very nice looking project. But
Hashing passwords with SHA256 alone is not sufficient for secure password storage. Here's why:
1. Speed: SHA256 is designed to be fa…
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**Type of issue**: Bug Report
**Please provide the steps to reproduce the problem:**
I assign 2 readwrite ports(aka Dual Port in ASIC) in the chisel(as well as the metadata), I tied off the `write…
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# Description
You can use OpenLane2 to convert your Verilog file to a GDSII Layout file. You can refer to [this](https://openlane2.readthedocs.io/en/latest/)
# Notes:
- You are eligible to get br…
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https://github.com/Nitheeshkumar521/asic-design-class/blob/main/asiclab1image.jpeg
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Hi all,
What are the minimum requirements of a SERV core to design a many-core ASIC using ASAP7 predictive PDK? I'm thinking about something like SMP architecture and I'm going to use [OpenSoC Fabric…