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Your website mentions the fifo module for axil, but it is nowhere to be found. Does it exist?
![Screenshot from 2024-08-23 16-53-12](https://github.com/user-attachments/assets/4448556a-5dd4-4b08-82fd…
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The description of the FIFO full and empty flags is wrong. According to the current `tidbits.md`:
> - FIFO FULL is set when the two indices are identical after a write, and reset when the indices s…
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another swreg type : FIFO , automatically inserts FULL, EMPTY , LEVEL etc
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Would it be possible to do the same thing here, but as a freight platform? Currently, freight platforms suffer from being LIFO just as containers do, which cause the same inherent limitations.
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## Description
Pérdida de datos en FIFO. Error al configurar tiempos de reloj diferentes.
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The actor framework needs to process the request it receives in sequential order. i.e FIFO has to be maintained while processing in Actor Service. Actor service can receive multiple concurrent request…
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### What's hard to do? (limit 100 words)
The way we set channel fifo depth doesn't feel coherent w/ the rest of DSLX syntax
Depth is currently set as the second arg of the channel type declaration…
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When I use the latest [marcos_extras](https://github.com/vnegnev/marcos_extras) such as branch [vn/mimo](https://github.com/vnegnev/marcos_extras/tree/vn/mimo)
or a self compiled FPGA bit file, [vn/…
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Firstly, this project is real neat.
Any thoughts on supporting FIFO queues with message key values, similar to SQS FIFO + MessageGroupId ?
Riffing off your existing work, here are the prototype …
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I would like to use fastp with input coming over a fifo. Since you're a single pass tool, it appears this should work. But no matter how I try to set things up, I get
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[2024-07-15T17:46:51-05…