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Currently ``apio time`` is not implemented for the ECP5 and Gowin families. This issue is for implementing them.
Timing verification is important to confirm that the synthesized code is within the…
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This issue is for adding to the``test-examples`` directory a test example for an Gowin board. Currently the testing of apio for Gowin is limited.
https://github.com/FPGAwars/apio/tree/develop/tes…
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Gowin FPGA chips have open source toolchain support. Boards as sipeed tang nano 9k are cheap and powerfull, but proprietary chinese IDE is drawback. Would it be possible to add support for them? They …
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in the article ( https://qiita.com/T_ksy/items/71e269da4fa06ec5c024 ) was said that the project was written in Gowin EDA, but I cannot run the project, I suspect that the .gprj file is missing, can yo…
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### Version
Yosys 0.42+12 (git sha1 62bff3a20, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
try to synthesize the output of litex
…
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Hi guys,
When run synthsizing of the nestang_nano20k.gprj, I got the following error
```
ERROR (RP0006) : The number(27765(26541 LUTs, 882 ALUs, 0 ROM16s, 57 SSRAMs)) of logic in the design exceeds…
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While running it as
> ./litex-boards/litex_boards/targets/sipeed_tang_nano_20k.py --toolchain=apicula --build
getting this error
```
INFO:SoC:Initializing ROM rom with contents (Size: 0x64e…
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Hi,
Your blog has very interesting information, I'm stating with FPGA and helped me a lot. I have a Tang Nano 4K.
I'm starting using this FPGA boards, I'm a bit newbie with all this FPGA, I was…
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After seeing that the Gowin IDE had a project for the Tang9K I tried building this and got a couple of errors. I include the log file and before making changes I just wanted to make sure that I am not…
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I am thinking to port this project to GOWIN GW2AR-18 FPGA
Got new board for it https://github.com/AI6YP/goryn
Where do you recommend to start?
drom updated
5 months ago