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Are there any plans to improve the coverage of documentation for ARTIQ/misoc/migen?
The ARTIQ user-facing documentation is generally pretty good. But, as soon as one wants to look at how things are…
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I am opening this issue to investigate allowing fusesoc to integrate migen or nmigen packages. I think this is a desirable functionality by several people.
Preliminarily, are there any high-level i…
FFY00 updated
3 years ago
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The AXI streams exposed by the on Ultrascale (+) PHYs are not standardized TLPs. To support the Ultrascale (+) PHYs in LitePCIe (that operates on standardized TLPs), the AXI streams have been adapted …
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This isn't necessarily a bug, but I do feel it makes Verilog identifiers that Migen generates more difficult to read.
Migen has a tendency to decorate Verilog identifiers with the `__main__` prefix i…
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Hello,
I'm trying to import verilog code into migen design as below:
First I created shifter.v:
```verilog
module shifter(
input sck_i,
input sdi_i,
output sdo_o,
input csn_i,
);…
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This issue concerns the [Migen/LiteX](https://github.com/im-tomu/fomu-workshop/blob/master/docs/migen.rst) page of thu tutorial.
It was not clear where I had to copy paste the extra Python code for…
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```
~/Build/Source/urukul ((v1.3.1) $%)$ python urukul_sim.py
Traceback (most recent call last):
File "urukul_sim.py", line 130, in
main()
File "urukul_sim.py", line 126, in main
sp…
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I have this test design for GTP transceivers, which contains
a counter and LEDs driven by the TX clock.
Unfortunately with this kind of writing the migen code:
https://github.com/openXC7/primitive-…
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As far as I can tell, migen.actorlib is no longer a thing?
https://github.com/m-labs/misoc/blob/master/misoc/cores/framebuffer/format.py#L6