issues
search
m-labs
/
misoc
The original high performance and small footprint system-on-chip based on Migen™
https://m-labs.hk
Other
305
stars
86
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
Updated EEM FMC Carrier target for v1.1
#148
kaolpr
closed
1 month ago
0
Remove xbuild, update llvm_asm macro to asm
#147
Spaqin
closed
1 month ago
0
pip install of tag 0.12 fails
#146
shareefj
opened
7 months ago
5
Kc705: mmcm_locked -> self.mmcm.locked in RtioSysCRG and add optional ext_async_rst to AsyncResetSynchronizerBUFG
#145
linuswck
closed
8 months ago
0
Kasli: mmcm_locked -> self.mmcm.locked in RtioSysCRG and add optional ext_async_rst to AsyncResetSynchronizerBUFG
#144
linuswck
closed
8 months ago
0
efc: add support for custom platform name
#143
linuswck
closed
9 months ago
1
EFC: Fix sys4x MMCM reset
#142
occheung
closed
10 months ago
0
EFC: Add comments regarding clk200 & OOB reset
#141
occheung
closed
10 months ago
0
EFC: Remove unused pll_clk125 signal
#140
occheung
closed
10 months ago
0
EFC: Expose reset signal to external source
#139
occheung
closed
10 months ago
0
Add virtual leds on efc target
#138
linuswck
closed
10 months ago
0
EFC/Kasli: Add sys5x clock domain
#137
occheung
closed
11 months ago
1
[WIP] Remove clock switch for EEM FMC Carrier
#136
occheung
closed
11 months ago
1
Configuration of IBUFDS_GTE2 was updated.
#135
den512is
closed
1 year ago
0
Add EEM FMC Carrier Support
#134
occheung
closed
1 year ago
0
[WIP] Kc705 clk merge
#133
Spaqin
closed
1 year ago
0
kasli: allow more configuration for _RtioSysCRG
#132
Spaqin
closed
1 year ago
0
misoc@2022-04-07 fail with either latest migen built from source (2022-09-02) and with migen 0.9.2
#131
doronbehar
closed
1 year ago
1
Added support for Digilent Genesys 2 target
#130
kaolpr
opened
1 year ago
3
SYS/RTIO clock merge
#129
Spaqin
closed
1 year ago
5
cpu_interface: add dmb() support
#128
Spaqin
closed
2 years ago
1
libunwind: Suppress compilation warning
#127
occheung
closed
2 years ago
0
SoCCore: Re-expose CSR address width parameter
#126
occheung
closed
2 years ago
0
VexRiscv: Add cores with FPU and/or 64-bits
#125
occheung
closed
2 years ago
0
Implement datapath support for 64-bits IBus/DBus
#124
occheung
closed
2 years ago
0
VexRiscv: Enable Physical Memory Protection (PMP)
#123
occheung
closed
2 years ago
0
vexriscv: Build Rust library with cargo-xbuild
#122
occheung
closed
2 years ago
0
vexriscv: update core
#121
occheung
closed
2 years ago
0
VexRiscv: Add Rust, LLVM support
#120
occheung
closed
2 years ago
0
(fd)libm: add RISC-V target to the list of little endian targets
#119
occheung
closed
2 years ago
0
spi_flash: Add little endian support
#118
occheung
closed
2 years ago
0
liteeth: Add little endian target support
#117
occheung
closed
2 years ago
0
ICAP: talk to ICAP primitive to restart gateware
#116
SidaChen1999
closed
2 years ago
1
unwinder: Fix resumption from unwinder for OR1K
#115
occheung
closed
2 years ago
0
Add updated libunwind with RV32 support
#114
occheung
closed
2 years ago
4
VexRiscv: Update to support atomic instructions
#113
occheung
closed
2 years ago
0
vexriscv: use clang
#112
occheung
closed
2 years ago
1
vexriscv: make bios big-endian
#111
occheung
closed
2 years ago
0
ICAP: talk to ICAPE2 primitive to restart gateware
#110
SidaChen1999
closed
2 years ago
0
spi2: allow optional CS pin in SPIInterface
#109
drewrisinger
opened
3 years ago
0
liteeth: Fix Kintex UltraScale GTH intermittent breakage
#108
HarryMakes
closed
3 years ago
2
Proposal for Some Quality of Life Improvements
#107
HarryMakes
opened
3 years ago
0
Updating submodules configuration after llvm changes
#106
mghibaudi
closed
3 years ago
0
liteeth: Fix missing auto-negotiation restart & improper logic for config_reg detection
#105
HarryMakes
closed
3 years ago
1
integration: create and run top-level Makefile for all software_packages
#104
astro
closed
3 years ago
0
csr: Proposal to accept CSRs with the same name owned by different submodules
#103
HarryMakes
opened
3 years ago
3
different clocking of differentiator and integrator
#102
nkrackow
closed
3 years ago
3
liteeth: Add support for 10/100Mbps via SGMII
#101
HarryMakes
closed
3 years ago
4
Wrong version in `setup.py`
#100
FFY00
closed
4 years ago
0
cores: replace use of add_sources(), remove use of add_verilog_include_path()
#99
astro
closed
4 years ago
0
Next