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m-labs
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misoc
The original high performance and small footprint system-on-chip based on Migen™
https://m-labs.hk
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spi2: add iCE40 differential interface
#98
airwoodix
closed
5 years ago
9
soc_core:allocate correct size for ROM.
#97
keesj
opened
5 years ago
0
register_rom weirdness
#96
keesj
opened
5 years ago
2
CSRStorage with write_from_dev=True seems broken in simulation
#95
mithro
opened
5 years ago
3
Use wrap_ts function to wrap signals of core that need tristate output.
#94
Fatsie
closed
5 years ago
1
Wanted to Build a small SoC
#93
bhatmahadev6
closed
5 years ago
1
fix or remove Ultrascale SDRAM init
#92
sbourdeauducq
closed
1 year ago
4
software not rebuilt after gateware change
#91
danielkucera
opened
5 years ago
0
added support for qm_xc6slx16_sdram board
#90
danielkucera
closed
5 years ago
0
bios: added debug info about flashboot source
#89
danielkucera
closed
5 years ago
9
added spi 1-bit mode, code from litex
#88
danielkucera
opened
5 years ago
6
Standard 1 bit SPI mode for spi_flash not available?
#87
danielkucera
opened
5 years ago
2
Added missing default argument
#86
kaolpr
closed
6 years ago
3
Support for AFC 3v1
#85
kaolpr
closed
5 years ago
2
Fix repetition in README.
#84
mgielda
closed
6 years ago
1
Binutils compilation
#83
danielkucera
opened
6 years ago
0
Obtain gateware toolchain path from environment variable
#82
kaolpr
closed
6 years ago
5
correctly use result of Record.connect in Converter
#81
tpwrules
closed
6 years ago
1
Record.connect return value not used
#80
tpwrules
closed
6 years ago
3
Sayma: remove unnecessary LOCs
#79
hartytp
closed
6 years ago
5
VexRiscv integration
#78
Dolu1990
closed
6 years ago
13
make SPI2 work for busses with no MOSI (e.g. ADCs like Sampler)
#77
hartytp
closed
6 years ago
1
spi: first half-cycle (setup period) of a chained, pure read uses the write divider instead of the read divider
#76
jordens
closed
6 years ago
0
DDR3-related error in Vivado timing report for Ultrascale
#75
sbourdeauducq
closed
6 years ago
1
kasli/spi_flash: investigate and implement quad i/o read
#74
jordens
opened
6 years ago
0
clean up memory regions, names, offsets
#73
jordens
opened
6 years ago
0
liteeth: remove MII clock output
#72
sbourdeauducq
opened
6 years ago
0
liteeth: rename dv to rx_dv
#71
sbourdeauducq
closed
6 years ago
0
liteeth: remove dw parameterization
#70
sbourdeauducq
closed
6 years ago
2
fix liteeth error counter atomicity problem
#69
sbourdeauducq
opened
6 years ago
2
replace liteeth _preamble_crc CSR with constant
#68
sbourdeauducq
closed
6 years ago
0
remove gap checker from liteeth
#67
sbourdeauducq
closed
6 years ago
1
flterm: memory leak
#66
jbqubit
closed
6 years ago
7
SPI clock glitches on CS transitions
#65
jordens
closed
6 years ago
0
liteeth should be tolerant to truncated or garbled preambles
#64
jordens
closed
6 years ago
1
DDR3 broken on some Sayma boards
#63
sbourdeauducq
closed
6 years ago
5
check that liteeth MAC observes minimum interframe gap
#62
jordens
closed
6 years ago
1
Compiling gcc-7.2.0
#61
FelixVi
closed
6 years ago
5
Papilio pro default rom size is too small
#60
FelixVi
closed
5 years ago
8
Paths broken when using Cygwin and Xilinx tools in Windows
#59
FelixVi
closed
6 years ago
1
cross check SPI core w.r.t. Vivado changes
#58
jordens
opened
6 years ago
0
merge a7ddrphy and k7ddrphy
#57
sbourdeauducq
opened
6 years ago
5
Bunch of small fixes
#56
mithro
opened
6 years ago
0
RGMII on Sayma broken
#55
jordens
closed
5 years ago
8
Gigabit ethernet PHY for serial links/SFP
#54
jordens
closed
6 years ago
2
support 4 byte spi flash addressing
#53
jordens
opened
6 years ago
1
error: Could not find a version that satisfies the requirement asyncserial (from miso c) (from versions: )
#52
erickson-nist
closed
6 years ago
6
remove FlipFlop
#51
sbourdeauducq
opened
6 years ago
0
setup.py fails on Ubuntu 16.04
#50
John-K
opened
7 years ago
2
Specify Python version 3.5 specifically
#49
ghost
closed
7 years ago
1
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