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m-labs
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misoc
The original high performance and small footprint system-on-chip based on Migen™
https://m-labs.hk
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Create a "spi settings" type thing (in same vein as the SDRAM settings)
#48
mithro
opened
7 years ago
2
Adding documentation to the csr modules.
#47
mithro
closed
7 years ago
0
Framebuffer core depends on migen.actorlib
#46
mithro
opened
7 years ago
1
Adding some documentation to code_8b10b.py
#45
mithro
closed
7 years ago
2
remove converter reset from liteeth mii.py
#44
sbourdeauducq
opened
7 years ago
0
define stream behavior when stb=0 and eop=1
#43
sbourdeauducq
opened
7 years ago
2
Wishbone SRAM: support memories larger than the bus width
#42
sbourdeauducq
opened
7 years ago
0
move liteeth FullMemoryWE transform to migen.build
#41
sbourdeauducq
opened
7 years ago
0
minicon: avoid oversized address signal
#40
sbourdeauducq
opened
7 years ago
0
liteeth: safe detection of oversized frames
#39
sbourdeauducq
closed
7 years ago
3
BIOS should use '\r\n' line endings
#38
mithro
opened
8 years ago
0
asyncserial dependency not documented
#37
ghost
closed
8 years ago
2
Avoid building all software packages for simple SoCs
#36
enjoy-digital
closed
8 years ago
1
Usage of symlinks on Windows is not convenient
#35
enjoy-digital
closed
8 years ago
3
clean up SDRAM module system
#34
sbourdeauducq
closed
8 years ago
7
CSR should have read and write swapped to master perspective
#33
sbourdeauducq
opened
8 years ago
0
^C shouldn't crash flterm
#32
whitequark
closed
8 years ago
2
improve packet delineation in streams
#31
sbourdeauducq
closed
8 years ago
2
improve SoC CSR scanning
#30
sbourdeauducq
closed
7 years ago
0
replacement necessary for flterm --serial-boot
#29
whitequark
closed
8 years ago
1
flterm broken when run under SSH
#28
whitequark
closed
8 years ago
5
flterm should send characters immediately, not after user presses return
#27
sbourdeauducq
closed
8 years ago
7
python setup.py install works without git submodule being initialized
#26
mithro
opened
8 years ago
5
Add CSRConstant
#25
sbourdeauducq
closed
8 years ago
0
new misoc: building fails on windows with Vivado
#24
enjoy-digital
closed
8 years ago
2
new misoc: building with lm32 fails on windows with ISE & Vivado
#23
enjoy-digital
closed
8 years ago
9
new misoc: build libdyld and libunwind only when needed
#22
enjoy-digital
closed
8 years ago
1
new misoc: symlinks on windows
#21
enjoy-digital
closed
8 years ago
2
migen verilog output is dependent on PYTHONHASHSEED
#20
mithro
closed
8 years ago
5
misoc should put all temporary and build assets in a separate directory
#19
mithro
closed
8 years ago
2
Add init file in sdram/phy dir
#18
rohitk-singh
closed
8 years ago
2
misoc (re)organization
#17
jordens
closed
8 years ago
28
UART: Evaluate irq conditions and choose the best
#16
enjoy-digital
closed
8 years ago
1
Improve simulator compatibility
#15
olofk
closed
9 years ago
1
Misc fixes
#14
olofk
closed
9 years ago
1
Remove litescope references from UART
#13
sbourdeauducq
closed
9 years ago
7
Use asyncio in flterm instead of threads
#12
sbourdeauducq
closed
8 years ago
6
spiflash.c wait_for_device_ready never returns on KC705
#11
sbourdeauducq
closed
9 years ago
4
add SPIFLASH_PAGE_SIZE and SPIFLASH_SECTOR_SIZE defines to pipistrello
#10
sbourdeauducq
closed
9 years ago
0
liteeth: MII clock frequency detection is hacky and unreliable
#9
sbourdeauducq
closed
9 years ago
5
Setup instructions don't include initializing git submodules and misoc gives a cryptic error
#8
mithro
closed
8 years ago
0
It would be nice to have a CONTRIBUTING file
#7
mithro
closed
9 years ago
1
First step in quick start guide doesn't link to further setup instructions for migen
#6
mithro
closed
9 years ago
2
LiteEth: Add support for RGMII phy interface
#5
mithro
closed
8 years ago
3
LiteEth: Add support for Digilent Atlys board
#4
mithro
closed
9 years ago
5
Xilinx ISE 14.7 (64-Bit) HDL compiler error / clog2 function
#3
nanosonde
closed
8 years ago
3
Adding git submodule init to README
#2
mithro
closed
9 years ago
2
Some Makefile love
#1
fallen
closed
11 years ago
0
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